PROG board: Difference between revisions

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==PROG8M42==
==PROG8M42==
==PROGBK1==
==PROGBK1==
The only non-protected board that can bankswitch and use all V ROM space. Really common and very useful for homebrew stuff or converts.
The only non-protected board that can bankswitch and use all [[V ROM]] space. Really common and very useful for homebrew stuff or converts.


===P ROM===
===P ROM===


P1 can be 4Mbit, 8Mbit or 16Mbit (27C400/27C800/27C160).
The [[P ROM|P1 ROM]] can be 4Mbit, 8Mbit or 16Mbit (27C400/27C800/27C160).
*If P1 is 16Mbit then some jumper must be set (JB3? didn't look into it. see kof95) and P2 should be empty.  First half of P1 is mapped to 0x200000-0x2FFFFF and second half is mapped to 0x000000-0x0FFFFFF.
*If P1 is 16Mbit then some jumper must be set (JB3? didn't look into it. see kof95) and P2 should be empty.  First half of P1 is mapped to 0x200000-0x2FFFFF and second half is mapped to 0x000000-0x0FFFFFF.
*If P1 is 4Mbit or 8Mbit, then P2 can contain a bankswitched ROM (same type as P1 plus 27C322).  P1 appears at 0x000000-0x0FFFFF.  P2 banked rom appears in 0x200000-0x2FFFFF.
*If P1 is 4Mbit or 8Mbit, then P2 can contain a bankswitched ROM (same type as P1 plus 27C322).  P1 appears at 0x000000-0x0FFFFF.  P2 banked rom appears in 0x200000-0x2FFFFF.


===V ROM===
[[Bankswitching]] is done with the LS74. It's not needed if the game isn't banked.  Any write to an odd address in the [[68k memory map|0x200000~0x2FFFFF]] range will set the bank. 512KiB banks ?
 
V ROMs can be 8Mbit, 16Mbit or 32Mbit (27C800/27C160/27C322).  Size of largest ROM is selected with a pair of jumpers and the other 4 should be left unconnected.  4Mbit can also be used but only if there is one ROM and only in the last used slot.
 
{| class="wikitable"
|-
!ROM size
!Jumper A
!Jumper B
|-
|8Mbit
|JV1
|JV2
|-
|16Mbit
|JV3
|JV4
|-
|32Mbit
|JV5
|JV6
|}
 
===Pinouts===
 
[[Bankswitching]] is done with the LS74. It's not needed if the game isn't banked.  Any write to an odd 0x200000-0x2FFFFF address will set the bank.
   
   
{| class="wikitable"
{| class="wikitable"
Line 144: Line 119:
|}
|}


One of 4 V ROMs is enabled with a set of LS139 outputs. The pair of V ROM jumpers effectively choose a set of 2 NEO-PCM address outputs to input to the LS139.
===V ROM===
 
[[File:Progbk1v.png]]
 
There is a maximum of 4 [[V ROM]]s which can be 8Mbit, 16Mbit or 32Mbit (27C800/27C160/27C322) for a maximum total size of 4 * 4MiB = 16MiB.
 
A 4Mbit ROM can also be used, but only if there's one and only if it's in the last used slot.
 
The size of the largest V ROM is selected with a pair of jumpers on 6 spots (3 possible choices).


{| class="wikitable"
{| class="wikitable"
|-
|-
!Jumper
!Largest V ROM
!LS139
!Jumper set
!V ROM
|-
|-
|JV1
|8Mbit (1MiB)
|2(1A)
|JV1+JV2
|N/A
|-
|-
|JV2
|16Mbit (2MiB)
|3(1B)
|JV3+JV4
|N/A
|-
|-
|JV3
|32Mbit (4MiB)
|2(1A)
|JV5+JV6
|N/A
|-
|JV4
|3(1B)
|N/A
|-
|JV5
|2(1A)
|N/A
|-
|JV6
|3(1B)
|N/A
|-
|N/A
|4(1Y0)
|V1 13(/OE)
|-
|N/A
|5(1Y1)
|V2 13(/OE)
|-
|N/A
|6(1Y2)
|V3 13(/OE)
|-
|N/A
|7(1Y3)
|V4 13(/OE)
|}
|}


The LS08 is used to AND the two PORT /OE signals.
This pair of V ROM jumpers effectively choose a set of 2 of the [[PCM]] chip address outputs to input to the LS139, which will enable one out of the 4 V ROMs at a time.
 
The JV7 to JV14 jumpers need to be set according to the ROM types. If it's less than 32Mbit, the JV7/JV8/JV9/JV10 jumper needs to be set (ground). If it's 32Mbit, the JV11/JV12/JV13/JV14 needs to be set (A20). This is because 32Mbit chips have their /BYTE pin replaced by A20.
 
===Other===
 
The LS08 is used to AND the /PORTOEU and /PORTOEL signals to get a /PORTOE.


*4x 1/2/4MiB V ROMs
*4x 1/2/4MiB V ROMs
Line 199: Line 156:
*1/2/4MiB P2 ROM
*1/2/4MiB P2 ROM
*2x 512KiB EP1/EP2 ROM
*2x 512KiB EP1/EP2 ROM
*NEO-PCM
*[[PCM]] chip
*LS139,LS08,LS74
*LS139,LS08,LS74
==PROGBK2==
==PROGBK2==
Looks identical to PROGBK1 in terms of ROM layout but uses a [[NEO-PCM2]] for encryption plus all other logic that was done with discrete chips on PROGBK1.
Looks identical to PROGBK1 in terms of ROM layout but uses a [[NEO-PCM2]] for encryption plus all other logic that was done with discrete chips on PROGBK1.

Revision as of 18:26, 6 April 2012


Cartridge PCB which holds the P and V ROMs.

List from [MAME's source].

MVS

Name Test Max P ROM Max V ROM
NPS-PRG1 [[UPD4990], BR4090, PCM
PROG-8MB
PROG-EP
PROG-G2 PCM,SNK-9201 512*2(+/?)1024
PROG-HERO
PROG-NAM
PROG16
PROG4096 PCM 2*512+1024+2048 3*2048
PROG4096B
PROG42G
PROG42G-1 PCM 128+1024 4*1024
PROG42G-COM
PROG8M42
PROGBK1
PROGBK2
PROGBK2R
PROGBK2S
PROGBK3R
PROGBK3S
PROGEOP
PROGGSC
PROGLBA
PROGTOP
PROGV
PROGMC2 PCM 8192 8192

NPS-PRG1

Neo Print cartridge. Has an UPD4990 and a BR4090 serial EEPROM.

PROG-8MB

PROG-EP

J1/J2: ROMWAIT (B25) on cart edge.

PROG-G2

PROG-HERO

PROG-NAM

PROG16

PROG4096

PROG4096B

PROG42G

PROG42G-1

PROG42G-COM

PROG8M42

PROGBK1

The only non-protected board that can bankswitch and use all V ROM space. Really common and very useful for homebrew stuff or converts.

P ROM

The P1 ROM can be 4Mbit, 8Mbit or 16Mbit (27C400/27C800/27C160).

  • If P1 is 16Mbit then some jumper must be set (JB3? didn't look into it. see kof95) and P2 should be empty. First half of P1 is mapped to 0x200000-0x2FFFFF and second half is mapped to 0x000000-0x0FFFFFF.
  • If P1 is 4Mbit or 8Mbit, then P2 can contain a bankswitched ROM (same type as P1 plus 27C322). P1 appears at 0x000000-0x0FFFFF. P2 banked rom appears in 0x200000-0x2FFFFF.

Bankswitching is done with the LS74. It's not needed if the game isn't banked. Any write to an odd address in the 0x200000~0x2FFFFF range will set the bank. 512KiB banks ?

Cart edge LS74 P2
A5(68k D0) 2(D1) N/A
A6(68k D1) 12(D2) N/A
A28(PORTWEL) 3(CLK1) N/A
A28(PORTWEL) 11(CLK2) N/A
N/A 5(Q1) 42(A19)
N/A 9(Q2) 32(A20)

V ROM

There is a maximum of 4 V ROMs which can be 8Mbit, 16Mbit or 32Mbit (27C800/27C160/27C322) for a maximum total size of 4 * 4MiB = 16MiB.

A 4Mbit ROM can also be used, but only if there's one and only if it's in the last used slot.

The size of the largest V ROM is selected with a pair of jumpers on 6 spots (3 possible choices).

Largest V ROM Jumper set
8Mbit (1MiB) JV1+JV2
16Mbit (2MiB) JV3+JV4
32Mbit (4MiB) JV5+JV6

This pair of V ROM jumpers effectively choose a set of 2 of the PCM chip address outputs to input to the LS139, which will enable one out of the 4 V ROMs at a time.

The JV7 to JV14 jumpers need to be set according to the ROM types. If it's less than 32Mbit, the JV7/JV8/JV9/JV10 jumper needs to be set (ground). If it's 32Mbit, the JV11/JV12/JV13/JV14 needs to be set (A20). This is because 32Mbit chips have their /BYTE pin replaced by A20.

Other

The LS08 is used to AND the /PORTOEU and /PORTOEL signals to get a /PORTOE.

  • 4x 1/2/4MiB V ROMs
  • 1/2MiB P1 ROM
  • 1/2/4MiB P2 ROM
  • 2x 512KiB EP1/EP2 ROM
  • PCM chip
  • LS139,LS08,LS74

PROGBK2

Looks identical to PROGBK1 in terms of ROM layout but uses a NEO-PCM2 for encryption plus all other logic that was done with discrete chips on PROGBK1.

PROGBK2R

PROGBK2S

PROGBK3R

PROGBK3S

PROGEOP

PROGGSC

PROGLBA

PROGSM

PROGSS3

PROGSF1

PROGTOP

PROGV (Brezzasoft)

Same board manufacturer as SNK ?

  • 42pin V1 and P1 ROMs (DIP or TSOP)
  • 64KiB Battery-backed RAM (Mapped to $200000~?)
  • External I/O port (8 ?)
  • Room for 2x8DIP switchs

PROGMC2(Prototype Board)

[Billy Pit's Neo-Geo Proto Page] or [[1]]

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