YM2610 bus timing

File:Ym2610timing.png

ADPCM-A ROM access

The access to the V ROMs are done sequentialy (in the channels order ?). A 666kHz clock is derived from the 8MHz main clock by dividing it by 12. This times the access steps:

• Rising edge: The first address bits are set
• Rising edge: SDRMPX goes high
• Falling edge A: The first address bits are latched in cartridge
• Rising edge: The last address bits are set
• Rising edge: SDRMPX goes low
• Falling edge B: The last address bits are latched in cartridge
• Rising edge C: /SDROE goes low, RAD0~7 is tristated
• One clock pulse to wait for ROM
• Falling edge D: ROM data is read

A complete read takes 9us. SDRMPX is 3us high, 6us low. /SDROE is 3us low, 6us high.

ADPCM-B ROM access

The access to the V ROMs are done synchronously with the ADPCM-A access. A 4MHz clock is derived from the 8MHz main clock. This times the access steps:

• Rising edge: The first address bits are set
• Rising edge: SDPMPX goes high
• Falling edge E: The first address bits are latched in cartridge
• Rising edge: The last address bits are set
• Rising edge: SDPMPX goes low
• Falling edge F: The last address bits are latched in cartridge
• Rising edge G: /SDPOE goes low, PAD0~7 is tristated
• One clock pulse to wait for ROM
• Falling edge H: ROM data is read

A complete read takes 1.5us. SDPMPX is 500ns high, /SDPOE is 500ns low. Reads can happen every 2 ADPCM-A read at most (gives a 55.5kHz samplerate).