68k instructions timings: Difference between revisions

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TODO: CSS template for cputiming is ugly and broken.
Mirroring information from http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML
Mirroring information from http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML


The number of bus read and write cycles is shown in parenthesis as (r/w).
In the following tables the headings have the following meanings:
* An : Address register operand
* Dn : Data register operand
* ea : Operand specified by an effective address
* M : Memory effective address operand


== Effective Address Operand Calculation Timing ==
To get the execution time, multiply the cycle count by 83.33ns ([[Clock|1/12MHz]]).


<syntaxhighlight lang="text">
This table lists the number of clock periods required to compute an
instruction's effective address. It includes fetching of any extension
words, the address computation , and fetching of the memory operand.
The number of bus read and write cycles is shown in parenthesis as (r/w).
Note there are no write cycles involved in processing the effective address.




Effective Address Calculation Times
=Effective address operand calculation=


register Byte,Word Long
This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.


Dn data register direct 0(0/0) 0(0/0)
Note: there are no write cycles involved in processing the effective address.
An address register direct 0(0/0) 0(0/0)
memory


(An) address register indirect 4(1/0) 8(2/0)
{|class="cputiming"
(An)+ address register indirect with post- 4(1/0) 8(2/0)
|'''Syntax'''
increment
|'''Adressing mode'''
-(An) address register indirect with predec. 6(1/0) 10(2/0)
|'''B,W'''
d(An) address register indirect with dis- 8(2/0) 12(3/0)
|'''L'''
placement
|-
d(An,ix) address register indirect with index 10(2/0) 14(3/0)
|Dn
xxx.W absolute short 8(2/0) 12(3/0)
|Data register direct
xxx.L absolute long 12(3/0) 16(4/0)
|style="background-color:#7F7;"|0(0/0)
d(PC) program counter with displacement 8(2/0) 12(3/0)
|style="background-color:#7F7;"|0(0/0)
d(PC,ix) program counter with index 10(2/0) 14(3/0)
|-
#xxx immediate 4(1/0) 8(2/0)
|An
|Address register direct
|style="background-color:#7F7;"|0(0/0)
|style="background-color:#7F7;"|0(0/0)
|-
|(An)
|Address register indirect
|4(1/0)
|8(2/0)
|-
|(An)+
|Address register indirect, post inc.
|4(1/0)
|8(2/0)
|-
| -(An)
|Address register indirect, pre dec.
|6(1/0)
|10(2/0)
|-
|d(An)
|Address register indirect, displacement
|8(2/0)
|12(3/0)
|-
|d(An,ix)
|Address register indirect, index
|10(2/0)
|14(3/0)
|-
|xxx.w
|Absolute short
|8(2/0)
|12(3/0)
|-
|xxx.l
|Absolute long
|style="background-color:#F77;"|12(3/0)
|style="background-color:#F77;"|16(4/0)
|-
|d(PC)
|PC with displacement
|8(2/0)
|12(3/0)
|-
|d(PC,ix)
|PC with index
|10(2/0)
|14(3/0)
|-
|#xxx
|Immediate
|4(1/0)
|8(2/0)
|}


The size of the index register (ix) does not affect execution time
The size of the index register (ix) does not affect execution time
</syntaxhighlight>




== Move Instruction Execution Times ==
=Move instructions=


<syntaxhighlight lang="text">
These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.
These following two tables indicate the number of clock periods for the move
instruction. This data includes instruction fetch, operand reads, and operand
writes. The number of bus read and write cycles is shown in parenthesis
as (r/w).


==Byte and word==


Move Byte and Word Instruction Execution Times
<syntaxhighlight lang="text">
 
     Dn An (An) (An)+ -(An) d(An) d(An,ix) xxx.W |xxx.L
     Dn An (An) (An)+ -(An) d(An) d(An,ix) xxx.W |xxx.L


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The size of the index register (ix) does not affect execution time
The size of the index register (ix) does not affect execution time
</syntaxhighlight>


==Long==


Move Long Instruction Execute Times
<syntaxhighlight lang="text">
 
     Dn An (An) (An)+ -(An) d(An) d(An,ix) xxx.W |xxx.L
     Dn An (An) (An)+ -(An) d(An) d(An,ix) xxx.W |xxx.L


Line 88: Line 138:




== Standard Instruction Execution Times ==
=Standard instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
The number of clock periods shown in this table indicates the time required
The number of clock periods shown in this table indicates the time required
to perform the operations, store the results and read the next instruction.
to perform the operations, store the results and read the next instruction.
The number of bus read and write cycles is shown in parenthesis as (r/w).
The number of clock periods and the number of read and write cycles must be
The number of clock periods and the number of read and write cycles must be
added respectively to those of the effective address calculation where  
added respectively to those of the effective address calculation where  
indicated.
indicated.
In the following table the headings have the following meanings:
An = address register operand, Dn = data register operand, ea = an operand
specified by an effective address, and M = memory effective address operand.
Standard Instruction Execution Times


instruction Size op<ea>,An ^ op<ea>,Dn op Dn,<M>
instruction Size op<ea>,An ^ op<ea>,Dn op Dn,<M>
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== Immediate Instruction Execution Times ==
=Immediate instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
The number of clock periods periods shown in this table includes the time to
The number of clock periods periods shown in this table includes the time to
fetch immediate operands, perform the operations, store the results and read  
fetch immediate operands, perform the operations, store the results and read  
the next operation. The number of bus read and write cycles is shown in
the next operation. The number of clock periods and the number of read and  
parenthesis as (r/w). The number of clock periods and the number of read and  
write cycles must be added respectively to those of the effective address
write cycles must be added respectively to those of the effective address
calculation where indicated.
calculation where indicated.
Immediate Instruction Execution Times


instruction size op #,Dn op #,An op #,M
instruction size op #,Dn op #,An op #,M
Line 183: Line 221:




== Single Operand Instruction Execution Times ==
=Single operand instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
This table indicates the number of clock periods for the single operand
This table indicates the number of clock periods for the single operand
instructions. The number of bus read and write cycles is shown in parenthesis
instructions. The number of clock periods and the number of read and write cycles
as (r/w). The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
must be added respectively to those of the effective address calculation
where indicated.
where indicated.
Single Operand Instruction Execution Times


instruction size register memory
instruction size register memory
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== Rotate Instruction Execution Times ==
=Shift and rotate instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
This table indicates the number of clock periods for the shift and rotate
This table indicates the number of clock periods for the shift and rotate
instructions. The number of read and write cycles is shown in parenthesis
instructions. The number of clock periods and the number of read and write
as (r/w). The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
cycles must be added respectively to those of the effective address
calculation where indicated.
calculation where indicated.
Shift/Rotate Instruction Execution Times


instruction size register memory
instruction size register memory
Line 238: Line 268:
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
  long 8+2n(1/0)   -
  long 8+2n(1/0)   -
ROXR,ROXl byte,word 6+2n(1/0) 8(1/1) +
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
  long 8+2n(1/0)   -
  long 8+2n(1/0)   -


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== Bit Manipulation Instruction Execution Times ==
=Bit manipulation instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
This table indicates the number of clock periods required for the bit
This table indicates the number of clock periods required for the bit
manipulation instructions. The number of read and write cycles is shown in
manipulation instructions. The number of clock periods and the number of read and  
parenthesis as (r/w). The number of clock periods and the number of read and  
write cycles must be added respectively to those of the effective address
write cycles must be added respectively to those of the effective address
calculation where indicated.
calculation where indicated. Dynamic: register, static: immediate.
 
 
Bit Manipulation Instruction Execution Times


instruction size dynamic static
instruction size dynamic static
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== Specificational Instruction Execution Times ==
=Conditional instructions=


<syntaxhighlight lang="text">
{|class="cputiming"
This table indicates the number of clock periods for the conditional
|'''Syntax'''
instructions. The number of read and write cycles is shown in parenthesis
|'''Displacement'''
as (r/w). The number of clock periods and the number of read and write
|'''Branch taken'''
cycles must be added respectively to those of the effective address
|'''Not taken'''
calculation where indicated.
|-
|rowspan=2|Bcc
|byte
|10(2/0)
|8(1/0)
|-
|word
|10(2/0)
|12(1/0)
|-
|rowspan=2|BRA
|byte
|10(2/0)
|
|-
|word
|10(2/0)
|
|-
|rowspan=2|BSR
|byte
|18(2/2)
|
|-
|word
|18(2/2)
|
|-
|rowspan=2|DBcc
|cc true
|
|12(2/0)
|-
|cc false
|10(2/0)
|style="background-color:#F77;"|14(3/0)
|}




Conditional Instruction Execution Times
=JMP, JSR, LEA, PEA and MOVEM instructions=
 
instruction displacement branch branch
taken not taken
 
Bcc byte 10(2/0) 8(1/0)
word 10(2/0) 12(1/0)
BRA byte 10(2/0)   -
word 10(2/0)   -
BSR byte 18(2/2)   -
word 18(2/2)   -
DBcc CC true   - 12(2/0)
CC false 10(2/0) 14(3/0)
</syntaxhighlight>
 
 
== JMP, JSR, LEA, PEA and MOVEM Instruction Execution Times ==


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
This Table indicates the number of clock periods required for the jump,
This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions. The number of bus read and write
move multiple registers instructions.
cycles is shown in parenthesis as (r/w).
 
 
JMP, JSR, LEA, PEA and MOVEM Instruction Execution Times


instr size (An) (An)+ -(An) d(An)
instr size (An) (An)+ -(An) d(An)
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== Multi-Precision Instruction Execution Times ==
=Multi-precision instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
Line 351: Line 393:
instructions. The number of clock periods includes the time to fetch both
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next  
operands, perform the operations, store the results and read the next  
instructions. The number of read and write cycles is shown in parenthesis
instructions.
as (r/w).
 
The headings have the following meanings: Dn = data register operand and
M = memory operand.
 
 
Multi-Presicion Instruction Execution Times


instruction size op Dn,Dn op M,M
instruction size op Dn,Dn op M,M
Line 373: Line 408:




== Miscellaneous Instruction Execution Times ==
=Miscellaneous instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
This table indicates the number of clock periods for the following  
This table indicates the number of clock periods for the following  
miscellaneous instructions. The number of bus read and write cycles is shown
miscellaneous instructions. The number of clock periods and plus the number
in parenthesis as (r/w). The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
of read and write cycles must be added to those of the effective address
calculation where indicated.
calculation where indicated.
Miscellaneous Instruction Execution Times


instruction size register memory
instruction size register memory
Line 417: Line 448:




== Move Peripheral Instruction Execution Times ==
=Move Peripheral instructions=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
Line 427: Line 458:




== Exception Processing Execution Times ==
=Exception processing=


<syntaxhighlight lang="text">
<syntaxhighlight lang="text">
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The number of clock periods includes the time for all stacking, the vector
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.
fetch and the fetch of the first two instruction words of the handler routine.
The number of bus read and write cycles is shown in parenthesis as (r/w).
Exception Processing Execution Times


exception periods
exception periods
Line 462: Line 489:


[[Category:Base system]]
[[Category:Base system]]
[[Category:Code]]

Revision as of 00:16, 24 February 2016

TODO: CSS template for cputiming is ugly and broken.

Mirroring information from http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/mc68000timing.HTML

The number of bus read and write cycles is shown in parenthesis as (r/w).

In the following tables the headings have the following meanings:

  • An : Address register operand
  • Dn : Data register operand
  • ea : Operand specified by an effective address
  • M : Memory effective address operand

To get the execution time, multiply the cycle count by 83.33ns (1/12MHz).


Effective address operand calculation

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

Note: there are no write cycles involved in processing the effective address.

Syntax Adressing mode B,W L
Dn Data register direct 0(0/0) 0(0/0)
An Address register direct 0(0/0) 0(0/0)
(An) Address register indirect 4(1/0) 8(2/0)
(An)+ Address register indirect, post inc. 4(1/0) 8(2/0)
-(An) Address register indirect, pre dec. 6(1/0) 10(2/0)
d(An) Address register indirect, displacement 8(2/0) 12(3/0)
d(An,ix) Address register indirect, index 10(2/0) 14(3/0)
xxx.w Absolute short 8(2/0) 12(3/0)
xxx.l Absolute long 12(3/0) 16(4/0)
d(PC) PC with displacement 8(2/0) 12(3/0)
d(PC,ix) PC with index 10(2/0) 14(3/0)
#xxx Immediate 4(1/0) 8(2/0)

The size of the index register (ix) does not affect execution time


Move instructions

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

Byte and word

     	 Dn	 An	 (An)	 (An)+	-(An)	 d(An)	d(An,ix) xxx.W	|xxx.L

Dn	 4(1/0)	 4(1/0)	 8(1/1)	 8(1/1)  8(1/1)	12(2/1) 14(2/1) 12(2/1) 16(3/1)
An	 4(1/0)	 4(1/0)	 8(1/1)	 8(1/1)	 8(1/1)	12(2/1) 14(2/1) 12(2/1) 16(3/1)
(An)	 8(2/0)	 8(2/0)	12(2/1) 12(2/1) 12(2/1) 16(3/1) 18(3/1) 16(3/1) 20(4/1)
(An)+	 8(2/0)	 8(2/0) 12(2/1) 12(2/1) 12(2/1) 16(3/1) 18(3/1) 16(3/1) 20(4/1)
-(An)	10(2/0) 10(2/0) 14(2/1) 14(2/1) 14(2/1) 18(3/1) 20(4/1) 18(3/1) 22(4/1)
d(An)	12(3/0) 12(3/0) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 22(4/1) 20(4/1) 24(5/1)
d(An,ix)14(3/0) 14(3/0) 18(3/1) 18(3/1) 18(3/1) 22(4/1) 24(4/1) 22(4/1) 26(5/1)
xxx.W	12(3/0) 12(3/0) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 22(4/1) 20(4/1) 24(5/1)
xxx.L	16(4/0) 16(4/0) 20(4/1) 20(4/1) 20(4/1) 24(5/1) 26(5/1) 24(5/1) 28(6/1)
d(PC)	12(3/0) 12(3/0) 16(3/1) 16(3/1) 16(3/1) 20(4/1) 22(4/1) 20(4/1) 24(5/1)
d(PC,ix)14(3/0) 14(3/0) 18(3/1) 18(3/1) 18(3/1) 22(4/1) 24(4/1) 22(4/1) 26(5/1)
#xxx	 8(2/0)	 8(2/0) 12(2/1) 12(2/1) 12(2/1) 16(3/1) 18(3/1) 16(3/1) 20(4/1)

The size of the index register (ix) does not affect execution time

Long

     	 Dn	 An	 (An)	 (An)+	-(An)	 d(An)	d(An,ix) xxx.W	|xxx.L

Dn	 4(1/0)	 4(1/0)	12(1/2)	12(1/2)	12(1/2)	16(2/2)	18(2/2)	16(2/2)	20(3/2)
An	 4(1/0)	 4(1/0)	12(1/2)	12(1/2)	12(1/2)	16(2/2)	18(2/2)	16(2/2)	20(3/2)
(An)	12(3/0)	12(3/0)	20(3/2)	20(3/2)	20(3/2)	24(4/2)	26(4/2)	24(4/2)	28(5/2)
(An)+	12(3/0)	12(3/0)	20(3/2)	20(3/2)	20(3/2)	24(4/2)	26(4/2)	24(4/2)	28(5/2)
-(An)	14(3/0)	14(3/0)	22(3/2)	22(3/2)	22(3/2)	26(4/2)	28(4/2)	26(4/2)	30(5/2)
d(An)	16(4/0)	16(4/0)	24(4/2)	24(4/2)	24(4/2)	28(5/2)	30(5/2)	28(5/2)	32(6/2)
d(An,ix)18(4/0)	18(4/0)	26(4/2)	26(4/2)	26(4/2)	30(5/2)	32(5/2)	30(5/2)	34(6/2)
xxx.W	16(4/0)	16(4/0)	24(4/2)	24(4/2)	24(4/2)	28(5/2)	30(5/2)	28(5/2)	32(6/2)
xxx.L	20(5/0)	20(5/0)	28(5/2)	28(5/2)	28(5/2)	32(6/2)	34(6/2)	32(6/2)	36(7/2)
d(PC)	16(4/0)	16(4/0)	24(4/2)	24(4/2)	24(4/2)	28(5/2)	30(5/2)	28(5/2)	32(5/2)
d(PC,ix)18(4/0)	18(4/0)	26(4/2)	26(4/2)	26(4/2)	30(5/2)	32(5/2)	30(5/2)	34(6/2)
#xxx	12(3/0)	12(3/0)	20(3/2)	20(3/2)	20(3/2)	24(4/2)	26(4/2)	24(4/2)	28(5/2)

The size of the index register (ix) does not affect execution time


Standard instructions

The number of clock periods shown in this table indicates the time required
to perform the operations, store the results and read the next instruction.
The number of clock periods and the number of read and write cycles must be
added respectively to those of the effective address calculation where 
indicated.

instruction	Size		op<ea>,An ^	op<ea>,Dn	op Dn,<M>

ADD		byte,word	8(1/0) +	  4(1/0) +	 8(1/1) +
		  long		6(1/0) +**	  6(1/0) +**	12(1/2) +
AND		byte,word	   -		  4(1/0) +	 8(1/1) +
		  long		   -		  6(1/0) +**	12(1/2) +
CMP		byte,word	6(1/0) +	  4(1/0) +	   -
		  long		6(1/0) +	  6(1/0) +	   -
DIVS		    -		   -		158(1/0) +*	   -
DIVU		    -		   -		140(1/0) +*	   -
EOR		byte,word	   -		  4(1/0) ***	 8(1/1) +
		  long		   -		  8(1/0) ***	12(1/2) +
MULS		    -		   -		 70(1/0) +*	   -
MULU		    -		   -		 70(1/0) +*	   -
OR		byte,word	   -		  4(1/0) +**	 8(1/1) +
		  long		   -		  6(1/0) +**	12(1/2) +
SUB		byte,word	8(1/0) +	  4(1/0) +	 8(1/1) +
		  long		6(1/0) +**	  6(1/0) +**	12(1/2) +

notes:	+ Add effective address calculation time
	^ Word or long only
	* Indicates maximum value
       ** The base time of six clock periods is increased to eight		
	  if the effective address mode is register direct or 
	  immediate (effective address time should also be added)
      *** Only available effective address mode is data register direct
	  
	DIVS,DIVU - The divide algorithm used by the MC68000 provides less
		    than 10% difference between the best and the worst case
		    timings.
	MULS,MULU - The multiply algorithm requires 38+2n clocks where
		    n is defined as:
		MULU: n = the number of ones in the <ea>
		MULS: n = concatanate the <ea> with a zero as the LSB;
			  n is the resultant number of 10 or 01 patterns
			  in the 17-bit source; i.e., worst case happens
			  when the source is $5555


Immediate instructions

The number of clock periods periods shown in this table includes the time to
fetch immediate operands, perform the operations, store the results and read 
the next operation. The number of clock periods and the number of read and 
write cycles must be added respectively to those of the effective address
calculation where indicated.

instruction	size		op #,Dn		op #,An		op #,M

ADDI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
ADDQ		byte,word	 4(1/0)		8(1/0) *	 8(1/1) +
		  long		 8(1/0)		8(1/0)		12(1/2) +
ANDI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/1) +
CMPI		byte,word	 8(2/0)		  -		 8(2/0) +
		  long		14(3/0)		  -		12(3/0) +
EORI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
MOVEQ		  long		 4(1/0)		  -		   -
ORI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
SUBI		byte,word	 8(2/0)		  -		12(2/1) +
		  long		16(3/0)		  -		20(3/2) +
SUBQ		byte,word	 4(1/0)		8(1/0) *	 8(1/1) +
		  long		 8(1/0)		8(1/0)		12(1/2) +

	+ Add effective address calculation time
	* word only


Single operand instructions

This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.

instruction	size		register	 memory

CLR		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
NBCD		  byte		6(1/0)		 8(1/1) +
NEG		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
NEGX		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
NOT		byte,word	4(1/0)		 8(1/1) +
		  long		6(1/0)		12(1/2) +
Scc		byte,false	4(1/0)		 8(1/1) +
		byte,true	6(1/0)		 8(1/1) +
TAS #		  byte		4(1/0)		10(1/1) +
TST		byte,word	4(1/0)		 4(1/0) +
		  long		4(1/0)		 4(1/0) +

	+ add effective address calculation time
        # This instruction should never be used on the Amiga as its invisiable
          read/write cycle can disrupt system DMA.


Shift and rotate instructions

This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.

instruction	size		register	memory

ASR,ASL		byte,word	6+2n(1/0)	8(1/1) +
		  long		8+2n(1/0)	  -
LSR,LSL		byte,word	6+2n(1/0)	8(1/1) +
		  long		8+2n(1/0)	  -
ROR,ROL		byte,word	6+2n(1/0)	8(1/1) +
		  long		8+2n(1/0)	  -
ROXR,ROXL	byte,word	6+2n(1/0)	8(1/1) +
		  long		8+2n(1/0)	  -

	+ add effective address calculation time
	n is the shift or rotate count


Bit manipulation instructions

This table indicates the number of clock periods required for the bit
manipulation instructions. The number of clock periods and the number of read and 
write cycles must be added respectively to those of the effective address
calculation where indicated. Dynamic: register, static: immediate.

instruction	size		dynamic			static
			register   memory	register   memory	
BCHG		byte	   -	   8(1/1) +	   -	   12(2/1) +
		long	 8(1/0) *    -		12(2/0) *     -
BCLR		byte	   -	   8(1/1) +	   -	   12(2/1) +
		long	10(1/0) *    -		14(2/0) *     -
BSET		byte	   -	   8(1/1) +	   -	   12(2/1) +
		long	 8(1/0) *    -		12(2/0) *     -
BTST		byte	   -  	   4(1/0) +	   -	    8(2/0) +
		long	 6(1/0)	     -		10(2/0)       -

	+ add effective address calculation time
	* indicates maximum value


Conditional instructions

Syntax Displacement Branch taken Not taken
Bcc byte 10(2/0) 8(1/0)
word 10(2/0) 12(1/0)
BRA byte 10(2/0)
word 10(2/0)
BSR byte 18(2/2)
word 18(2/2)
DBcc cc true 12(2/0)
cc false 10(2/0) 14(3/0)


JMP, JSR, LEA, PEA and MOVEM instructions

This Table indicates the number of clock periods required for the jump,
jump-to-subroutine, load effective address, push effective address and
move multiple registers instructions.

instr	size	(An)		(An)+		-(An)	d(An)	
JMP	-	  8(2/0)	   -		  -	10(2/0)
JSR	-	 16(2/2)	   -		  -	18(2/2)
LEA	-	  4(1/0)	   -		  -	 8(2/0)
PEA	-	 12(1/2)	   -		  -	16(2/2)
MOVEM	word	   12+4n	   12+4n	  -	  16+4n
M->R		 (3+n/0)	 (3+n/0)	  -	(4+n/0)
	long	   12+8n	   12+8n	  -	  16+8n
		(3+2n/0)	(3+2n/0)	  -    (4+2n/0)
MOVEM	word	    8+4n	   -		  8+4n	  12+4n
R->M		   (2/n)	   -		 (2/n)	  (3/n)
	long	    8+8n	   -		  8+8n	  12+8n
		  (2/2n)	   -		(2/2n)	 (3/2n)

instr	size	d(An,ix)+   xxx.W      xxx.L      d(PC)      d(PC,ix)*
JMP	 -	 14(3/0)    10(2/0)    12(3/0)	  10(2/0)    14(3/0)
JSR	 -	 22(2/2)    18(2/2)    20(3/2)	  18(2/2)    22(2/2)
LEA	 -	 12(2/0)     8(2/0)    12(3/0)	   8(2/0)    12(2/0)
PEA	 -	 20(2/2)    16(2/2)    20(3/2)	  16(2/2)    20(2/2)
MOVEM	word	   18+4n      16+4n      20+4n	    16+4n      18+4n
M->R		 (4+n/0)    (4+n/0)    (5+n/0)	  (4+n/0)    (4+n/0)
	long	   18+8n      16+8n      20+8n	    16+8n      18+8n
		(4+2n/0)   (4+2n/0)   (5+2n/0)	 (4+2n/0)   (4+2n/0)
MOVEM	word	   14+4n      12+4n      16+4n	    -		-
R->M		   (3/n)      (3/n)      (4/n)	    -		-
	long	   14+8n      12+8n      16+8n	    -		-
		  (3/2n)     (3/2n)     (4/2n)	    -		-

n is the number of registers to move
* is the size of the index register (ix) does not affect the instruction's
  execution time


Multi-precision instructions

This table indicates the number of clock periods for the multi-precision
instructions. The number of clock periods includes the time to fetch both
operands, perform the operations, store the results and read the next 
instructions.

instruction	size		op Dn,Dn	op M,M

ADDX		byte,word	4(1/0)		18(3/1)
		  long		8(1/0)		30(5/2)
CMPM		byte,word	  -		12(3/0)
		  long		  -		20(5/0)
SUBX		byte,word	4(1/0)		18(3/1)
		  long		8(1/0)		30(5/2)
ABCD		  byte		6(1/0)		18(3/1)
SBCD		  byte		6(1/0)		18(3/1)


Miscellaneous instructions

This table indicates the number of clock periods for the following 
miscellaneous instructions. The number of clock periods and plus the number
of read and write cycles must be added to those of the effective address
calculation where indicated.

instruction	size	register	memory

ANDI to CCR	byte	 20(3/0)	   -
ANDI to SR	word	 20(3/0)	   -
CHK		 -	 10(1/0) +	   -
EORI to CCR	byte	 20(3/0)	   -
EORI to SR	word	 20(3/0)	   -
ORI to CCR	byte	 20(3/0)	   -
ORI to SR	word	 20(3/0)	   -
MOVE from SR	 -	  6(1/0)	 8(1/1)+
MOVE to CCR	 -	 12(1/0)	12(1/0)+
MOVE to SR	 -	 12(1/0)	12(1/0)+
EXG		 -	  6(1/0)	   -
EXT		word	  4(1/0)	   -
		long	  4(1/0)	   -
LINK		 -	 16(2/2)	   -
MOVE from USP	 -	  4(1/0)	   -
MOVE to USP	 -	  4(1/0)	   -
NOP		 -	  4(1/0)	   -
RESET		 -	132(1/0)	   -
RTE		 -	 20(5/0)	   -
RTR		 -	 20(5/0)	   -
RTS		 -	 16(4/0)	   -
STOP		 -	  4(0/0)	   -
SWAP		 -	  4(1/0)	   -
TRAPV (No Trap)	 -	  4(1/0)	   -
UNLK		 -	 12(3/0)	   -

	+ add effective address calculation time


Move Peripheral instructions

instruction	size	register->memory	memory->register

MOVEP		word	16(2/2)			16(4/0)	
		long	24(2/4)			24(6/0)


Exception processing

This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.

	exception			periods

	address error			50(4/7)
	bus error			50(4/7)
	CHK instruction (trap taken)	44(5/3)+
	Divide by Zero			42(5/3)
	illegal instruction		34(4/3)
	interrupt			44(5/3)*
	privilege violation		34(4/3)
        _____
	RESET **			40(6/0)
	trace				34(4/3)
	TRAP instruction		38(4/3)
	TRAPV instruction (trap taken)	34(4/3)

	+ add effective address calculation time
	* the interrupt acknowledge cycle is assumed to take four
	  clock periods
                                       _____     ____
       ** indicates the time from when RESET and HALT are first
	  sampled as negated to when instruction execution starts
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