Revision as of 21:37, 21 February 2017

Chip found on late MVS boards and next to the DIP switches on ROM-Only boards.

Pinout

Todo: COUNT* are outputs. BOARD go to the vertical board on MV1B.

DIPRD0 and DIPRD1 go to a NEO-BUF chip to gate the remaining DIP switch bits and RTC inputs
Pin 85 might be an input
Some BOARD pins must be ROMOE*, PORTOE*, PORTWE*... SFIX select...
No memory card control signals ?

@@ Line 8: / Line 8: @@
 }}
-Picture courtesy of [[http://www.mvs-scans.com MVS-Scans]].
+Chip found on late [[MVS hardware|MVS]] boards and next to the [[Hardware DIPs|DIP switches]] on [[ROM-Only boards]].
-Chip found on late [[MVS hardware|MVS]] boards and next to the [[Hardware DIPs|DIP switches]] on [[ROM-Only boards]].
+* Address decoding
+* Coin I/O
+* [[Memory_mapped_registers#System_registers|System register]]
+* [[Wait state]] generator
 =Pinout=
-Todo.
+Todo: COUNT* are outputs. BOARD go to the vertical board on MV1B.
+[[File:Neo-dcr_pinout.png]]
+Draft pinout: [[File:neo-dcr.odg]]
+* DIPRD0 and DIPRD1 go to a {{Chipname|NEO-BUF}} chip to gate the remaining DIP switch bits and RTC inputs
+* Pin 85 might be an input
+* Some BOARD pins must be ROMOE*, PORTOE*, PORTWE*... SFIX select...
+* No [[memory card]] control signals ?
 [[Category:Chips]]