NEO-CMC: Difference between revisions

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OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]
OpenOffice Draw file: [[File:Neocmc_7050_7042.odg]]


Signals:
'''Signals:'''
*C_e_D[0..15]: C odd data bus
CXe_D[0..15]: C odd data bus
*C_o_D[0..15]: C even data bus
CXo_D[0..15]: C even data bus
*CX A[0..21]: C1~8 address bus
CX_A[0..21]: C1~8 address bus
*Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
*Pins 89 and 92 are shorted.
Pin 32 connects power Power System Reset (PST600D) to reset the NEOCMC decryption in case of power failure.
Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins 89 and 92 are shorted.
Pin 147 is used only in MVS and AES relase (2003.7.24) as  M1_CE else release is NC
 
'''NOTE:''' NEO-CMC is interchangeable between boards ([[CHAFIO]]) even between MVS to AES. Between them the way to delivery Graphic Information is different but is present inside the CMC(40/50).
 
[[Category:Chips]]
[[Category:Chips]]

Revision as of 15:55, 18 July 2023

Package QFP180
Manufacturer
First use 1999 ?
Used on CHAFIO...
File:Brd cmcnoref.jpg
"CMC50"

Late SNK custom chip used for protection, bankswitching and latching on CHAFIO CHA boards.

Descrambling/decryption infos can be found in [MAME:prot_cmc.c]

Versions

This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.

The datasheet apparently can't be found anymore for any of the known types:

  • TC190G06CF7008
  • TC190G06CF7042
  • TC190G06CF7050

(probably others...)

SNK merged the following designs into this chip:

  • NEO-ZMC
  • NEO-273
  • PRO-CT0
  • New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.

The first released NEO-MVS CHAFIO PCBs came out with the 042 version of NEO-CMC, on the following cartridges:

On this version only the S1 and C ROMs are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the 050 reference and was found in the following cartridges:

Until today, nobody has released a cloned chip on the underground market.

Fix handling

See fix bankswitching.

Encryption

Todo.

Pinout

OpenOffice Draw file: File:Neocmc 7050 7042.odg

Signals:

CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus

Pin 32 connects power Power System Reset (PST600D) to reset the NEOCMC decryption in case of power failure.
Pins 87,88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins 89 and 92 are shorted.
Pin 147 is used only in MVS and AES relase (2003.7.24) as  M1_CE else release is NC
NOTE: NEO-CMC is interchangeable between boards (CHAFIO) even between MVS to AES. Between them the way to delivery Graphic Information is different but is present inside the CMC(40/50).