NEO-I0

NEO-I0 chip found on a MV2B MVS board.

MVS specific chip that does a bunch of unrelated things.

• S ROM address latch for SFIX, same as S ROM portion of NEO-273
• SM1 /CS output when Z80 is reading from ROM and SM1/SFIX is enabled (SM1CS = SDROM OR SYSTEM)
• /ROMOE output for cartridge PROG board (ROMOE = ROMOEU AND ROMEOU)
• Video sync output for JAMMA edge
• Coin counter and coin lockout output

Pinout

File:Neo-i0 pinout.png

OpenOffice Draw file: File:Neo-i0.odg

• P0~P15: GPU multiplexed bus.

On a MV1F:

• Q00~Q18 are connected to the SFIX ROM address lines.
• SM1CS(ORO0) = SYSTEM(ORI0) OR SDROM(ORI1)
• SYNCOUT = SYNCIN XOR SYNCREV ?
• Q21, Q22: METER1, METER2
• Q23, Q24: LOCK1, LOCK2