NEO-E0

NEO-E0 chip found on a AES board.

MVS specific chip.

BIOS vector table swapping

When 68k A8~A23 = 0 and the BIOS's vector table is chosen (by using REG_SWPBIOS or REG_SWPROM), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a BIOS access instead of a P ROM access.

User:Kyuusaku: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}

On the AES, the AND gate is used for /SROMOE from /SROMOEL AND /SROMOEU.

MV2B @ H7 pinout

55 = sPCK1B 56 = sPCK2B

MV2B @ G2 pinout

OpenOffice Draw file: File:Neo-e0 mv2b G2.odg

A1~A23: 68k address bus MCA0~MCA23: memory card address bus BNK0~BNK2: memory card banking from NEO-D0 VEC: BIOS vector table swapping enable

MV2B @ F7 pinout

OpenOffice Draw file: File:Neo-e0 mv2b F7.odg

Acts just as a buffer. s*: signals to both slots

Pinout

OpenOffice Draw file: File:Neo-e0.odg

A1~A23: 68k address bus Y0~Y23: memory card address bus BNK0~BNK2: comes from NEO-D0, memory card banking VEC: BIOS vector table swapping enable ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL