68k exception handling

See 68k vector table.

Divide by zero/Illegal instruction

(DIVU or DIVS by zero, or bad opcode)

6 bytes stack frame: 0:SR.w, 2:PC.l

ErrDivZero:
    move.l  2(a7),PCERROR
    movem.l d0-d7/a0-a6,-(a7)
    lea     ERR_DIVZERO,a0
    jmp     DispErr

Address error/Bus error

(Misaligned read/writes, hardware fault ?)

14 bytes stack frame: 0:R/W.w, 2:Access address.l, 6:Instruction.l, 8:SR.w, 10:PC.l

ErrAddr:
    move.l  10(a7),PCERROR
    movem.l d0-d7/a0-a6,-(a7)
    lea     ERR_ADDR,a0
    jmp     DispErr

Displaying for debug

Don't forget to mask out all interrupts as soon as an exception is raised:

    ori.w   #$0700,sr

All register values can be retrieved from the previous MOVEMs and displayed on the fix layer:

;D0: 32bit value
;VRAM address needs to be set before
Write32bit:
    move.w  #$20,VRAM_MOD
    move.l  d0,d1
    move.l  #8-1,d7
.writerlp:
    move.b  d0,REG_DIPSW   ;Watchdog
    andi.l  #$F0000000,d0  ;x0000000
    lsl.l   #4,d0          ;0000000x
    jsr     .hexshift
    addi.w  #ASCIISTART,d0
    ori.w   #$F000,d0      ;Palette $F
    move.w  d0,VRAM_RW
    lsl.l   #4,d1
    move.l  d1,d0
    dbra    d7,.writerlp
    rts

.hexshift:
    cmp.b   #$A,d0
    blt.b   .r
    addq.b  #7,d0
.r:
    rts