Graphic glitches
This is supposed to be a repair guide that doesn't need much technical knowledge on the GFX hardware to understand. Only cart systems are covered here. Pics are provided for all glitches described and can be used to compare glitches that show up on faulty hardware for help in repairs.
todo: maybe add more detail, get rest of pics/descriptions up
..don't have any LSPC-A0 info to work with so only LSPC2 is included for now
C ROM
C ROM address
C ROM address lines follow this path:
- LSPC2/LSPC-A0 to CHA slot (on multislots it will go through some buffers in between)
- CHA slot to 74273 or similar(on oldest games)/NEO-273(on most games)/NEO-CMC(on newest games)
- 273/CMC to C ROM address lines
See pinouts for the slot pin numbers of the P0~23/CA4 signals listed in the table.
Lower address lines
A stuck lower address line for C ROMs causes certain patterns with display glitches. The graphics appear to be selected correctly but are glitched in various ways. A bad trace in the path of pins listed in the table can cause the glitch shown in the sample pic.
| Sample | Address | LSPC2 out | NEO‑273 in | NEO‑273 out | C ROMs in | Notes |
|---|---|---|---|---|---|---|
 |
A0 | P16(134) | P16(57) | C_A0(64) | A0(10) | 1 row of pixels mirrored. Sprites appear "pixelated" as if it's lower res. |
 |
A1 | P17(135) | P17(59) | C_A1(1) | A1(9) | Sets of 2 rows are mirrored. |
 |
A2 | P18(136) | P18(25) | C_A2(32) | A2(8) | Sets of 4 rows are mirrored. |
 |
A3 | P19(137) | P19(27) | C_A3(33) | A3(7) | Sets of 8 rows are mirrored. |
 |
A4 | CA4(102) | N/A | N/A | A4(6) | Sets of 8 columns are mirrored. Note NEO-273 isn't used and CA4 on CHA connector goes straight to C ROM A3. |
Higher address lines
Higher address lines can cause the 16x16 blocks of sprite graphics to appear without glitches but in completely wrong places. C ROM address A5 upwards can cause this. The patterns aren't obvious like they are for lower address lines so it's not as easy to diagnose. The sample pic to the right shows an example. Graphics from different stages, characters etc. can show up correctly but are misplaced.
C ROM data
jailbars..
S ROM
S ROM address
Lower address lines
...
| Sample | Address | LSPC2 out | NEO‑273 in | NEO‑273 out | S ROM in | Notes |
|---|---|---|---|---|---|---|
 |
A0 | P12(126) | P12(52) | S_A0(48) | A0(12) | 1 row of pixels mirrored. Appears "pixelated". |
 |
A1 | P13(128) | P13(53) | S_A1(49) | A1(11) | Sets of 2 rows mirrored. |
 |
A2 | P14(129) | P14(54) | S_A2(50) | A2(10) | Sets of 4 rows mirrored. |
 |
A3 | 2H1(107) | N/A | N/A | A3(9) | Sets of 2 columns mirrored. CHA 2H1 goes straight to A3 on S ROM. |
 |
A4 | P15(130) | P15(55) | S_A4(51) | A4(8) | Sets of 4 columns mirrored. |
S ROM data
jailbars..