YM2610 registers

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Pages detailing the different YM2610 parts:

Reading

The only writable registers that can be read back are the SSG ones. To read register X, write X to Z80 port 4, then read Z80 port 5.

Z80 port Data Notes
$04
Bit 7 6 5 4 3 2 1 0
Def Busy -Timer B flagTimer A flag
When a timer expires and IRQ is enabled for that timer, the respective flag is set.
$05
Bit 7 6 5 4 3 2 1 0
Def SSG register data
Attempting to read non-SSG registers will return 0.
$06
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B end -CH6 endCH5 endCH4 endCH3 endCH2 endCH1 end
When a channel has reached the end address and stops, the respective bit is set (unless masked).
$07 Not implemented Always returns $00

Map

This is a quick reference table to help visualize the whole chip mapping, check the main YM2610 pages for a more complete information about registers.

CHx stands for channel x, OPx for operator x.

Color codes:

SSG
FM
TIMERS
ADPCM
Unused/Test


Port 0 (Z80 writes to port 4/5) Port 1 (Z80 writes to port 6/7)
0x00 CHA
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Bit 7 6 5 4 3 2 1 0
Def Dump -CH6 ONCH5 ONCH4 ONCH3 ONCH2 ON CH1 ON
0x01
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
Bit 7 6 5 4 3 2 1 0
Def - Master volume
0x02 CHB
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Bit 7 6 5 4 3 2 1 0
Def ?
0x03
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
0x04 CHC
Bit 7 6 5 4 3 2 1 0
Def Fine tune
0x05
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
0x06 Noise
Bit 7 6 5 4 3 2 1 0
Def - Noise tune
0x07
Bit 7 6 5 4 3 2 1 0
Def - /EN noise C/EN noise B/EN noise A/EN tone C/EN tone B/EN tone A
0x08 CHA
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Bit 7 6 5 4 3 2 1 0
Def L R-Channel volume
CH1
0x09 CHB
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
CH2
0x0a CHC
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
CH3
0x0b
Bit 7 6 5 4 3 2 1 0
Def Volume envelope period fine tune
CH4
0x0c
Bit 7 6 5 4 3 2 1 0
Def Volume envelope period coarse tune
CH5
0x0d
Bit 7 6 5 4 3 2 1 0
Def - Volume envelope shape
CH6
0x0e
0x0f
0x10
Bit 7 6 5 4 3 2 1 0
Def Start -Repeat-Reset
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 LSB
CH1
0x11
Bit 7 6 5 4 3 2 1 0
Def L R-
CH2
0x12
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 LSB
CH3
0x13
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 MSB
CH4
0x14
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 LSB
CH5
0x15
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 MSB
CH6
0x16
0x17
0x18
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 MSB
CH1
0x19
Bit 7 6 5 4 3 2 1 0
Def Delta-N (L)
CH2
0x1a
Bit 7 6 5 4 3 2 1 0
Def Delta-N (H)
CH3
0x1b
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B channel volume
CH4
0x1c
Bit 7 6 5 4 3 2 1 0
Def B -A6A5A4A3A2A1
CH5
0x1d CH6
0x1e
0x1f
0x20
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 LSB
CH1
0x21
Bit 7 6 5 4 3 2 1 0
Def ?
CH2
0x22
Bit 7 6 5 4 3 2 1 0
Def - OnControl
CH3
0x23 CH4
0x24
Bit 7 6 5 4 3 2 1 0
Def TA counter load bits MSBs
CH5
0x25
Bit 7 6 5 4 3 2 1 0
Def - TA counter load bits LSBs
CH6
0x26
Bit 7 6 5 4 3 2 1 0
Def TB counter load
0x27
Bit 7 6 5 4 3 2 1 0
Def CSM mode 2CH modeFlag reset TBFlag reset TAEnable TB IRQEnable TA IRQLoad TBLoad TA
0x28
Bit 7 6 5 4 3 2 1 0
Def Slot -Channel
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 MSB
CH1
0x29 CH2
0x2a CH3
0x2b CH4
0x2c CH5
0x2d CH6
0x2e
0x2f
0x30
0x31 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def - DTMUL
CH3/OP1
0x32 CH2/OP1 CH4/OP1
0x33
0x34
0x35 CH1/OP3 CH3/OP3
0x36 CH2/OP3 CH4/OP3
0x37
0x38
0x39 CH1/OP2 CH3/OP2
0x3a CH2/OP2 CH4/OP2
0x3b
0x3c
0x3d CH1/OP4 CH3/OP4
0x3e CH2/OP4 CH4/OP4
0x3f
0x40
0x41 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def - Total Level
CH3/OP1
0x42 CH2/OP1 CH4/OP1
0x43
0x44
0x45 CH1/OP3 CH3/OP3
0x46 CH2/OP3 CH4/OP3
0x47
0x48
0x49 CH1/OP2 CH3/OP2
0x4a CH2/OP2 CH4/OP2
0x4b
0x4c
0x4d CH1/OP4 CH3/OP4
0x4e CH2/OP4 CH4/OP4
0x4f
0x50
0x51 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def KS -AR
CH3/OP1
0x52 CH2/OP1 CH4/OP1
0x53
0x54
0x55 CH1/OP3 CH3/OP3
0x56 CH2/OP3 CH4/OP3
0x57
0x58
0x59 CH1/OP2 CH3/OP2
0x5a CH2/OP2 CH4/OP2
0x5b
0x5c
0x5d CH1/OP4 CH3/OP4
0x5e CH2/OP4 CH4/OP4
0x5f
0x60
0x61 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def AM -DR
CH3/OP1
0x62 CH2/OP1 CH4/OP1
0x63
0x64
0x65 CH1/OP3 CH3/OP3
0x66 CH2/OP3 CH4/OP3
0x67
0x68
0x69 CH1/OP2 CH3/OP2
0x6a CH2/OP2 CH4/OP2
0x6b
0x6c
0x6d CH1/OP4 CH3/OP4
0x6e CH2/OP4 CH4/OP4
0x6f
0x70
0x71 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def - SR
CH3/OP1
0x72 CH2/OP1 CH4/OP1
0x73
0x74
0x75 CH1/OP3 CH3/OP3
0x76 CH2/OP3 CH4/OP3
0x77
0x78
0x79 CH1/OP2 CH3/OP2
0x7a CH2/OP2 CH4/OP2
0x7b
0x7c
0x7d CH1/OP4 CH3/OP4
0x7e CH2/OP4 CH4/OP4
0x7f
0x80
0x81 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def SL RR
CH3/OP1
0x82 CH2/OP1 CH4/OP1
0x83
0x84
0x85 CH1/OP3 CH3/OP3
0x86 CH2/OP3 CH4/OP3
0x87
0x88
0x89 CH1/OP2 CH3/OP2
0x8a CH2/OP2 CH4/OP2
0x8b
0x8c
0x8d CH1/OP4 CH3/OP4
0x8e CH2/OP4 CH4/OP4
0x8f
0x90
0x91 CH1/OP1
Bit 7 6 5 4 3 2 1 0
Def - SSG-EG
CH3/OP1
0x92 CH2/OP1 CH4/OP1
0x93
0x94
0x95 CH1/OP3 CH3/OP3
0x96 CH2/OP3 CH4/OP3
0x97
0x98
0x99 CH1/OP2 CH3/OP2
0x9a CH2/OP2 CH4/OP2
0x9b
0x9c
0x9d CH1/OP4 CH3/OP4
0x9e CH2/OP4 CH4/OP4
0x9f
0xa0
0xa1 CH1
Bit 7 6 5 4 3 2 1 0
Def F-Num 1
CH3
0xa2 CH2 /OP4 CH4
0xa3
0xa4
0xa5 CH1
Bit 7 6 5 4 3 2 1 0
Def - BlockF-Num 2
CH3
0xa6 CH2 / OP4 CH4
0xa7
0xa8 OP3
Bit 7 6 5 4 3 2 1 0
Def 2CH * F-Num 1
0xa9 OP1
0xaa OP2
0xab
0xac OP3
Bit 7 6 5 4 3 2 1 0
Def - 2CH * Block2CH * F-Num 2
0xad OP1
0xae OP2
0xaf
0xb0
0xb1 CH1
Bit 7 6 5 4 3 2 1 0
Def - FBALGO
CH3
0xb2 CH2 CH4
0xb3
0xb4
0xb5 CH1
Bit 7 6 5 4 3 2 1 0
Def L RAMS-PMS
CH3
0xb6 CH2 CH4
0xb7
0xb8
0xb9
... ...
0xfd
0xfe
0xff
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