NEO-CMC

Package	QFP180
Manufacturer
First use	1999 ?
Used on	CHAFIO...

File:Brd cmcnoref.jpg

"CMC50"

Late SNK custom chip used for protection, bankswitching and latching on CHAFIO CHA boards.

Descrambling/decryption infos can be found in [MAME:prot_cmc.c]

Versions

This chip is a TC190G series Toshiba ASIC developed between 1990 and 1994.

The datasheet apparently can't be found anymore for any of the known types:

• TC190G06CF7008
• TC190G06CF7042
• TC190G06CF7050

(probably others...)

SNK merged the following designs into this chip:

• NEO-ZMC
• NEO-273
• PRO-CT0
• New scrambling system that interlaces M1 + (C* + S1) to decrypt all the graphics ROMs data in real time.

The first released NEO-MVS CHAFIO PCBs came out with the 042 version of NEO-CMC, on the following cartridges:

• Zupapa!
• The King of Fighters '99 - Millennium Battle
• Ganryu
• Garou - Mark of the Wolves
• Strikers 1945 Plus
• Prehistoric Isle 2
• Metal Slug 3
• Bang Bead
• Nightmare in the Dark
• Sengoku 3

On this version only the S1 and C ROMs are encrypted and M1 remains unencrypted. Almost one year later, SNK decided to add one more layer, this time also encrypting M1. This new NEO-CMC chip had the 050 reference and was found in the following cartridges:

• Jockey Grand Prix
• The King of Fighters 2000
• The King of Fighters 2001
• Metal Slug 4
• Rage of the Dragons
• The King of Fighters 2002
• Matrimelee
• Pochi and Nyaa
• Metal Slug 5
• SNK vs. Capcom - SVC Chaos
• Samurai Shodown V
• The King of Fighters 2003
• Samurai Shodown V Special

Until today, nobody has released a cloned chip on the underground market.

Fix handling

See fix bankswitching.

Encryption

Todo.

Pinout

OpenOffice Draw file: File:Neocmc 7050 7042.odg

Signals:

CXe_D[0..15]: C odd data bus
CXo_D[0..15]: C even data bus
CX_A[0..21]: C1~8 address bus

Pin : 32 connects the Mitsumi (PST600D) reset generator to re-initialize the NEO-CMC in case of power failure.
Pins: 87 and 88 contains a RC circuit clock driver like in a 8085 with X1 and X2 pinouts
Pins: 89 and 92 are shorted.
Pin : 94 in MVS is NC and AES is connected again to 12M
Pin :147 is configured in:
     NEO-MVH MVOC   (2003.11.03) as M1_CE
     NEO-MVH MVOBR  (2003.08.04) as M1_CE
     NEO-MVS CHAFIO (2003.07.24) as M1_CE
     NEO-AEG CHAFIO (2003.07.24) as M1_CE
     NEO-MVS MVOB   (2003.07.09) as NC (but fixed by wirewrapps)
     NEO-MVS MVO    (2003.06.05) as NC
     NEO-MVS CHAFIO (1999.06.14) as NC
     NEO-AEG CHAFIO (1999.08.10) as NC
Pin : 152 is configured in:
     NEO-MVH (MVOC) as VCC
     NEO-MVH (MVO, MVOB, MVOBR) as GND
     NEO-MVS (ALL) as GND
     NEO-AEG (ALL) as GND  

NOTE1: There is no pinout differences between NEO-CMC42 and NEO-CMC50, however differences can be spotted between previous and later board releases with respect to some setup lines and pin 147. A substantial setup difference can be found comparing the boards of AES and MVS releases. The way the chip access and delivery the graphic data is different between them and both configurations is already available inside the NEO-CMC that is configured by the setup of the board itself. So the NEO-CMC is interchangeable between boards between MVS, AES and MVH embedded. See the releases at (CHAFIO)

NOTE2: In case somebody wonders, it's impossible to downgrade or upgrade NEO-CMCs between different versions (from 42 to 50 and vice-versa). The reason is that it's impossible without preparing the game for that and the algorithm to do it is unknown.