YM2610 bus timing
ADPCM-A bus
Access to the ADPCM-A ROMs for each channel is done sequentialy (in the channels order ?). A ~667kHz clock is derived from the YM2610's 8MHz clock by dividing it by 12.
- Period 0: The address LSBs are set
- Period 1: SDRMPX goes high
- Period 2: The address MSBs are set
- Period 3: SDRMPX goes low
- Period 4: SDROE goes low, RAD0~7 becomes hi-z
- Period 5: ROM outputs data (when is it latched ?)
Each period is 1.5us, a complete read cycle is 6 * 1.5 = 9us.
ADPCM-B bus
The access to the ADPCM-B ROMs is done synchronously with a 4MHz clock, derived from the 8MHz clock.
- Period 0: The address LSBs are set
- Period 1: SDPMPX goes high
- Period 2: The address MSBs are set
- Period 3: SDPMPX goes low
- Period 4: SDPOE goes low, PAD0~7 becomes hi-z
- Period 5: ROM outputs data (when is it latched ?)
Each period is 250ns, each complete read cycle is 6 * 250 = 1.5us. Reads can happen every 2 ADPCM-A read at most (gives a 55.5kHz samplerate).