MV2F

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Revised 2 slot board with the second generation chipset.

Pinouts

Z80

todo: formatting, maybe pics

Z80 A0~A15 to NEO-E0 @ K10:
Z80 A0(30) -> E0 A1(64)
Z80 A1(31) -> E0 A2(1)
Z80 A2(32) -> E0 A3(2)
Z80 A3(33) -> E0 A4(3)
Z80 A4(34) -> E0 A5(4)
Z80 A5(35) -> E0 A6(15)
Z80 A6(36) -> E0 A7(16)
Z80 A7(37) -> E0 A8(17)
Z80 A8(38) -> E0 A9(18)
Z80 A9(39) -> E0 A10(19)
Z80 A10(40) -> E0 A11(20)
Z80 A11(1) -> E0 A12(21)
Z80 A12(2) -> E0 A13(31)
Z80 A13(3) -> E0 A14(32)
Z80 A14(4) -> E0 A15(33)
Z80 A15(5) -> E0 A16(34)

NEO-E0 @ K10 to cart slots:
Y0~Y15 from this NEO-E0 go to SDA0~SDA15 on both cart slots (A43~A58 on the CHA connector)
Y0 -> #1 & #2 CHA A43(A0)
etc...
Y15 -> #1 & #2 CHA A58(A15)

Z80 D0~D7 multiplexed from NEO-257 @ J9:
Z80 D0(14) -> 257 Y8(40)
Z80 D1(15) -> 257 Y9(41)
Z80 D2(12) -> 257 Y10(43)
Z80 D3(8) -> 257 Y11(44)
Z80 D4(7) -> 257 Y12(55)
Z80 D5(9) -> 257 Y13(56)
Z80 D6(10) -> 257 Y14(59)
Z80 D7(13) -> 257 Y15(60)

NEO-257 @ J9 to cart slots:
257 A8(36) -> #1 CHA SDD0(B51)
257 B8(37) -> #2 CHA SDD0(B51)
257 A9(38) -> #1 CHA SDD1(B52)
257 B9(39) -> #2 CHA SDD1(B52)
etc...

NEO-D0 to NEO-E0 @ K10 to cart slots:
D0 SDROM(11) -> 257 /OE(33) (for Y8~Y15 atleast, labelled as "GND" on wiki seems to be the /OE)
D0 SDMRD(39) -> E0 A17(36)
D0 SDROM(11) -> E0 A18(37)
D0 SDRD0(45) -> E0 A19(38)
D0 SDRD1(46) -> E0 A20(48)
E0 Y16(39) -> #1 & #2 CHA SDMRD(B50)
E0 Y17(40) -> #1 & #2 CHA SDROM(B49)
E0 Y18(41) -> #1 & #2 CHA SDRD0(B47)
E0 Y19(43) -> #1 & #2 CHA SDRD1(B48)

NEO-F0 to NEO-257 @ J9:
F0 SLOTA(39) -> 257 SELECT(17)

(note "A1~A2"3 considered the 68k bus, probably named A0-A23 officially with "A0" unused on 1 slot)