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- *Max code ROM: '''2 MiB''' (without bankswitching) *Max FIX tileset: '''128 KiB''' (without bankswitching) ...682 bytes (98 words) - 08:21, 2 October 2016
- ...dress line are also used as data input. The chip's write strobe SDRD0 is [[Z80 port map|port]] address decoded inside the system. * SDA0, SDA1, SDA8~15: Z80 address bus ...2 KB (229 words) - 09:16, 28 January 2024
- *Acknowledge [[Z80 interrupts|NMI]] |Set [[Z80|window 0]] bank ...1 KB (210 words) - 09:19, 28 January 2024
- [[File:cd2_z80.jpg|right|thumb|Z80 in a surface mount package, as found on some MVS and CD boards.]] The Z80 is a 8-bit little-endian CPU designed by Zilog. ...4 KB (693 words) - 08:21, 28 January 2024
- See [[Z80/YM2610 interface]] and [[YM2610 registers]]. * {{Sig|SDD|SDD*}}: {{Chipname|Z80}} data bus ...4 KB (501 words) - 18:19, 26 July 2017
- | Second bank of the 68k program ROM (also used for bankswitching and access to special chips) | Z80 I/O ...3 KB (396 words) - 09:42, 8 October 2023
- *UV1: EPM3256 CPLD for [[V ROM]] bankswitching and {{Chipname|PCM}} replacement. JTAG port is JV1. ...ame will not have sound until system soft reset (probably due to corrupted Z80 ROM image). ...14 KB (2,189 words) - 13:15, 12 September 2020