Difference between revisions of "YM2610 registers"

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m (Created page with "= SSG part = thumb|right|Selectable EG shapes of the SSG {| class="regdef" |'''Address (Z80 port 4)''' |'''Data (Z80 port 5)''' | |- |$00 |{{8BitRegi…")
 
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= ADPCM-B part =
 
= ADPCM-B part =
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= Reading =
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The only writable registers that can also be read are from the SSG.  All other ports and addresses return different data.
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{| class="regdef"
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|'''Z80 port #'''
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|'''Data'''
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|Notes
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|-
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|$04
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|{{8BitRegister|Busy|1|-|5|Timer B end|1|Timer A end|1}}
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|When a timer expires and IRQ is enabled for the timer, the respective bit is set
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|-
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|$05
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|{{8BitRegister|SSG register data|8}}
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|Attempting to read non-SSG registers will fail
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|-
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|$06
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|{{8BitRegister|ADPCM-B end|1|-|1|CH6 end|1|CH5 end|1|CH4 end|1|CH3 end|1|CH2 end|1|CH1 end|1}}
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|When a channel has reached the end address and stops, the respective bit is set
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|-
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|$07
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|not implemented
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|Always returns $00
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|-
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|}
  
 
[[Category:CPUs]]
 
[[Category:CPUs]]
 
[[Category:Audio system]]
 
[[Category:Audio system]]

Revision as of 08:20, 27 February 2011

SSG part

Selectable EG shapes of the SSG
Address (Z80 port 4) Data (Z80 port 5)
$00
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Channel A
$01
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
$02
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Channel B
$03
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
$04
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Channel C
$05
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
$06
Bit 7 6 5 4 3 2 1 0
Def - Noise tune
Noise channel
$07
Bit 7 6 5 4 3 2 1 0
Def - /EN noise/EN A/EN B/EN C
$08
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Channel A
$09
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Channel B
$0A
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Channel C
$0B
Bit 7 6 5 4 3 2 1 0
Def Volume envelope period fine tune
$0C
Bit 7 6 5 4 3 2 1 0
Def Volume envelope period coarse tune
$0D
Bit 7 6 5 4 3 2 1 0
Def - Volume envelop shape
See diagram.

If 'Mode' = 1, the EG is used instead of the 4bit volume value. f = 8M / (Coarse*256 + Fine) ?

FM part

ADPCM-A part

'Dump' in register $00 is the key on/off bit. Write 0 to start playing specified channels and write 1 to stop playing.

Address (Z80 port 6) Data (Z80 port 7)
$00
Bit 7 6 5 4 3 2 1 0
Def Dump -CH6 ONCH5 ONCH4 ONCH3 ONCH2 ON CH1 ON
$01
Bit 7 6 5 4 3 2 1 0
Def - Master volume
$08~$0D (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def L R-Channel volume
$10~$15 (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 LSB
$18~$1D (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 MSB
$20~$25 (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 LSB
$28~$2D (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 MSB

ADPCM-B part

Reading

The only writable registers that can also be read are from the SSG. All other ports and addresses return different data.

Z80 port # Data Notes
$04
Bit 7 6 5 4 3 2 1 0
Def Busy -Timer B endTimer A end
When a timer expires and IRQ is enabled for the timer, the respective bit is set
$05
Bit 7 6 5 4 3 2 1 0
Def SSG register data
Attempting to read non-SSG registers will fail
$06
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B end -CH6 endCH5 endCH4 endCH3 endCH2 endCH1 end
When a channel has reached the end address and stops, the respective bit is set
$07 not implemented Always returns $00