YM2610 registers

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Summary: ...

Timers

See YM2610 timers.

SSG part

See SSG for details on this part's operation.

FM part

See FM for details on this part's operation.

Common FM registers

Address (Z80 port 4) Data (Z80 port 5)
$22
Bit 7 6 5 4 3 2 1 0
Def - OnControl
LFO Frequency
$28
Bit 7 6 5 4 3 2 1 0
Def Slot -Channel
Key On/Off

LFO frequency values are as follows:

  • 0 – 3.98Hz
  • 1 – 5.56Hz
  • 2 – 6.02Hz
  • 3 – 6.37Hz
  • 4 – 6.88Hz
  • 5 – 9.63Hz
  • 6 – 48.1Hz
  • 7 – 72.2Hz

Overall channel registers

The first value listed in the Address column is for channels 1/3; the second is for channels 2/4.

Address (Z80 port 4 or 6) Data (Z80 port 5 or 7)
$A1,$A2
Bit 7 6 5 4 3 2 1 0
Def F-Num 1
F-Numbers and Block (1/2)
$A5,$A6
Bit 7 6 5 4 3 2 1 0
Def - BlockF-Num 2
F-Numbers and Block (2/2)
(must set this first)
$A9,$AA
Bit 7 6 5 4 3 2 1 0
Def 2CH * F-Num 1
2CH - 2 Slot F-Numbers/Block (1/2)
$AD,$AE
Bit 7 6 5 4 3 2 1 0
Def - 2CH * Block2CH * F-Num 2
2CH - 2 Slot F-Numbers/Block (1/2)
(must set this first)
$B1,$B2
Bit 7 6 5 4 3 2 1 0
Def - FBALGO
Feedback (FB) and Algorithm (ALGO)
$B5,B6
Bit 7 6 5 4 3 2 1 0
Def L RAMS-PMS
Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)

Channel registers

Depending on which channel you want to write to, the ports used are different:

  • Channels 1 & 2: Ports 4/5
  • Channels 3 & 4: Ports 6/7

Per-operator registers

The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

Operator 1 2 3 4
Channels 1, 3 $x1 $x5 $x9 $xD
Channels 2, 4 $x2 $x6 $xA $xE
Address (Z80 port 4 or 6) Data (Z80 port 5 or 7)  
$31-$3E
Bit 7 6 5 4 3 2 1 0
Def - DTMUL
Detune (DT) and Multiple (MUL)
$41-$4E
Bit 7 6 5 4 3 2 1 0
Def - Total Level
Total Level (Volume)
$51-$5E
Bit 7 6 5 4 3 2 1 0
Def KS -AR
Key Scale (KS) and Attack Rate (AR)
$61-$6E
Bit 7 6 5 4 3 2 1 0
Def AM -DR
AM On (AM) and Decay Rate (DR)
$71-$7E
Bit 7 6 5 4 3 2 1 0
Def - SR
Sustain Rate (SR)
$81-$8E
Bit 7 6 5 4 3 2 1 0
Def SL RR
Sustain Level (SL) and Release Rate (RR)
$91-$9E
Bit 7 6 5 4 3 2 1 0
Def - SSG-EG
SSG-EG

ADPCM part

See ADPCM for details on this part's operation.

Reading

The only writable registers that can also be read are from the SSG. All other ports and addresses return different data.

Z80 port # Data Notes
$04
Bit 7 6 5 4 3 2 1 0
Def Busy -Timer B flagTimer A flag
When a timer expires and IRQ is enabled for the timer, the respective bit is set
$05
Bit 7 6 5 4 3 2 1 0
Def SSG register data
Attempting to read non-SSG registers will fail
$06
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B end -CH6 endCH5 endCH4 endCH3 endCH2 endCH1 end
When a channel has reached the end address and stops, the respective bit is set, unless masked
$07 not implemented Always returns $00