LSPC-A0: Difference between revisions

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(Created page with "=Pinout= 1:VCC 2:A1 3:A2 4:A3 5:D0 6:D1 7:D2 8:D3 9:D4 10:D5 11:D6 12:D7 13:D8 14:D9 15:D10 16:D11 17:D12 18:D13 19:GND 20:VCC 21:GND 22:D14 23:D15 24:Slow VRAM A0 25:Slow VR...")
 
 
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{{ChipInfo
|picture=Mvs_lspc-a0.jpg
|pkg=QFP160
|manu=nec
|date=1990 ?
|gates=
|used_on={{PCB|NEO-AES}} {{PCB|MV1}}
}}
LSPC-A0 is the [[VDC]] part of the first generation chipset, see {{Chipname|LSPC2-A2}} for more details.
=Pinout=
=Pinout=


1:VCC
*117: 8 ULN2803 K11 / 112 C0
2:A1
*127: C0 37/1 Ls273 E4/5
3:A2
*128: C0 54/B0 21
4:A3
 
5:D0
{{Pinout|LSPC-A0|640}}
6:D1
7:D2
8:D3
9:D4
10:D5
11:D6
12:D7
13:D8
14:D9
15:D10
16:D11
17:D12
18:D13
19:GND
20:VCC
21:GND
22:D14
23:D15
24:Slow VRAM A0
25:Slow VRAM A1
26:Slow VRAM A2
27:Slow VRAM A3
28:Slow VRAM A4
29:Slow VRAM A5
30:Slow VRAM A6
31:Slow VRAM A7
32:Slow VRAM A8
33:Slow VRAM A9
34:Slow VRAM A10
35:Slow VRAM A11
36:Slow VRAM A12
37:Slow VRAM A13
38:Slow VRAM A14
39:Slow VRAM D0
40:VCC


41:GND
*A1~A3: {{Chipname|68k}} address bus
42:GND
*D0~D15: 68k data bus
43:Slow VRAM D1
*SVA0~SVA14: Slow [[VRAM]] bank address bus
*SVD0~SVD15: Slow VRAM bank data bus
*FVA0~FVA10: Fast VRAM bank address bus
*FVD0~FVD15: Fast VRAM bank data bus


[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 01:08, 8 July 2018

Package QFP160
Manufacturer
First use 1990 ?
Used on NEO-AES MV1

LSPC-A0 is the VDC part of the first generation chipset, see LSPC2-A2 for more details.

Pinout

  • 117: 8 ULN2803 K11 / 112 C0
  • 127: C0 37/1 Ls273 E4/5
  • 128: C0 54/B0 21


Edit this pinout

  • A1~A3: 68k address bus
  • D0~D15: 68k data bus
  • SVA0~SVA14: Slow VRAM bank address bus
  • SVD0~SVD15: Slow VRAM bank data bus
  • FVA0~FVA10: Fast VRAM bank address bus
  • FVD0~FVD15: Fast VRAM bank data bus
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