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| | {{ChipInfo |
| | |picture=Mvs_lspc-a0.jpg |
| | |pkg=QFP160 |
| | |manu=nec |
| | |date=1990 ? |
| | |gates= |
| | |used_on={{PCB|NEO-AES}} {{PCB|MV1}} |
| | }} |
| | |
| | LSPC-A0 is the [[VDC]] part of the first generation chipset, see {{Chipname|LSPC2-A2}} for more details. |
| | |
| =Pinout= | | =Pinout= |
|
| |
|
| 1:VCC
| | *117: 8 ULN2803 K11 / 112 C0 |
| 2:A1
| | *127: C0 37/1 Ls273 E4/5 |
| 3:A2
| | *128: C0 54/B0 21 |
| 4:A3
| | |
| 5:D0 | | {{Pinout|LSPC-A0|640}} |
| 6:D1
| | |
| 7:D2
| | *A1~A3: {{Chipname|68k}} address bus |
| 8:D3
| | *D0~D15: 68k data bus |
| 9:D4
| | *SVA0~SVA14: Slow [[VRAM]] bank address bus |
| 10:D5
| | *SVD0~SVD15: Slow VRAM bank data bus |
| 11:D6
| | *FVA0~FVA10: Fast VRAM bank address bus |
| 12:D7
| | *FVD0~FVD15: Fast VRAM bank data bus |
| 13:D8
| |
| 14:D9
| |
| 15:D10
| |
| 16:D11
| |
| 17:D12
| |
| 18:D13
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| 19:GND
| |
| 20:VCC
| |
| 21:GND | |
| 22:D14
| |
| 23:D15
| |
| 24:Slow VRAM A0
| |
| 25:Slow VRAM A1
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| 26:Slow VRAM A2
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| 27:Slow VRAM A3
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| 28:Slow VRAM A4
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| 29:Slow VRAM A5
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| 30:Slow VRAM A6
| |
| 31:Slow VRAM A7
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| 32:Slow VRAM A8
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| 33:Slow VRAM A9
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| 34:Slow VRAM A10
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| 35:Slow VRAM A11
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| 36:Slow VRAM A12
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| 37:Slow VRAM A13
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| 38:Slow VRAM A14
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| 39:Slow VRAM D0 (K9)
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| 40:VCC
| |
| 41:GND
| |
| 42:GND
| |
| 43:Slow VRAM D1
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| 44:Slow VRAM D2
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| 45:Slow VRAM D3
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| 46:Slow VRAM D4
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| 47:Slow VRAM D5
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| 48:Slow VRAM D6
| |
| 49:Slow VRAM D7
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| 50:Slow VRAM D0 (L9)
| |
| 51:Slow VRAM D1
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| 52:Slow VRAM D2
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| 53:Slow VRAM D3
| |
| 54:Slow VRAM D4
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| 55:Slow VRAM D5
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| 56:Slow VRAM D6
| |
| 57:Slow VRAM D7
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| 58:Slow VRAM /OE
| |
| 59:Slow VRAM /RW
| |
| 60: 4
| |
| 61: 3
| |
| 62: BR2
| |
| 63: 1
| |
| 64: 2
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| 65: 3
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| 66: 4
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| 67: TR5 5814 bot
| |
| 68: 4
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| 69: 3
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| 70: BR2
| |
| 71: 1
| |
| 72: 2
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| 73: 3
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| 74: 4
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| 75: TR5 5814 top
| |
| 76: TL4 5814
| |
| 77: 8RB 68k
| |
| 78: 9RB 68k
| |
| 79: GND
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| 80: GND
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| 81: VCC
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| 82: 5RL LO
| |
| 83: 6
| |
| 84: 7
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| 85: 8
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| 86: 9
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| 87: 10
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| 88: 11
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| 89: 12
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| 90: 4/5/8 LU
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| 91: 4/5/8
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| 92: 4/5/8
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| 93: 6
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| 94: 2n 3LU
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| 95: pareil
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| 96: 2 LU
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| 97: 1n
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| 98:
| |
| 99: VCC
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| 100: GND
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| 101: VCC
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| 102: 3 N9
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| 103: 4 N9
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| 104: 7 N9
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| 105: 5 N10
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| 106: 16 N10
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| 107: 3 N10
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| 108: 6 P10
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| 109:
| |
| 110:
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| 111:
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| 112:
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| 113:
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| 114:
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| 115:
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| 116:
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| 117:
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| 118:
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| 119:
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| 120: VCC
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| [[Category:Chips]] | | [[Category:Chips]] |
Latest revision as of 01:08, 8 July 2018
|
| Package
|
QFP160
|
| Manufacturer
|
|
| First use
|
1990 ?
|
| Used on
|
NEO-AES MV1
|
LSPC-A0 is the VDC part of the first generation chipset, see LSPC2-A2 for more details.
Pinout
- 117: 8 ULN2803 K11 / 112 C0
- 127: C0 37/1 Ls273 E4/5
- 128: C0 54/B0 21
Edit this pinout
- A1~A3: 68k address bus
- D0~D15: 68k data bus
- SVA0~SVA14: Slow VRAM bank address bus
- SVD0~SVD15: Slow VRAM bank data bus
- FVA0~FVA10: Fast VRAM bank address bus
- FVD0~FVD15: Fast VRAM bank data bus
