Latest revision as of 01:08, 8 July 2018

LSPC-A0 is the VDC part of the first generation chipset, see LSPC2-A2 for more details.

Pinout

@@ Line 1: / Line 1: @@
-[[File:Mvs_lspc-a0.jpg|right|thumb|LSPC-A0 graphics chip found in on a MV4.]]
+{{ChipInfo
+|picture=Mvs_lspc-a0.jpg
+|pkg=QFP160
+|manu=nec
+|date=1990 ?
+|gates=
+|used_on={{PCB|NEO-AES}} {{PCB|MV1}}
+}}
-Part of the first generation [[GPU]], see [[LSPC2-A2]] for more details.
+LSPC-A0 is the [[VDC]] part of the first generation chipset, see {{Chipname|LSPC2-A2}} for more details.
-==Pinout==
+=Pinout=
-: 8 ULN2803 K11 / 112 C0
+*117: 8 ULN2803 K11 / 112 C0
+*127: C0 37/1 Ls273 E4/5
+*128: C0 54/B0 21
-: F7 LS86 12
+{{Pinout|LSPC-A0|640}}
-: C0 37/1 Ls273 E4/5
+*A1~A3: {{Chipname|68k}} address bus
+*D0~D15: 68k data bus
-: C0 54/B0 21
+*SVA0~SVA14: Slow [[VRAM]] bank address bus
-: 3 D7 (AS04)
-(Max size:[[:File:lspc-a0_pinout.png]])<br>
-[[File:lspc-a0_pinout.png|640px]]
-OpenOffice Draw file: [[File:lspc-a0.odg]]
-*A1~A3: [[68k]] address bus
-*D0~D15: [[68k]] data bus
-*SVA0~SVA14: Slow VRAM bank address bus
 *SVD0~SVD15: Slow VRAM bank data bus
 *FVA0~FVA10: Fast VRAM bank address bus
 *FVD0~FVD15: Fast VRAM bank data bus
-*LOA0~LOA15: [[LO ROM]] address bus ([[P bus]] ?)
-*DOTA/DOTB,H,LOAD: C ROM multiplexer control, see [[PRO-CT0]]
-*EVEN: Swap signal for dual pixel data
-*IP0/IP1:
 [[Category:Chips]]