LSPC-A0: Difference between revisions
Jump to navigation
Jump to search
mNo edit summary |
m (→Pinout) |
||
| (2 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{ChipInfo | |||
|picture=Mvs_lspc-a0.jpg | |||
|pkg=QFP160 | |||
|manu=nec | |||
|date=1990 ? | |||
|gates= | |||
|used_on={{PCB|NEO-AES}} {{PCB|MV1}} | |||
}} | |||
LSPC-A0 is the [[VDC]] part of the first generation chipset, see {{Chipname|LSPC2-A2}} for more details. | |||
=Pinout= | =Pinout= | ||
117: 8 ULN2803 K11 / 112 C0 | *117: 8 ULN2803 K11 / 112 C0 | ||
*127: C0 37/1 Ls273 E4/5 | |||
*128: C0 54/B0 21 | |||
127: C0 37/1 Ls273 E4/5 | |||
128: C0 54/B0 21 | |||
{{Pinout|LSPC-A0|640}} | |||
*A1~A3: {{Chipname|68k}} address bus | *A1~A3: {{Chipname|68k}} address bus | ||
*D0~D15: 68k data bus | *D0~D15: 68k data bus | ||
*SVA0~SVA14: Slow VRAM bank address bus | *SVA0~SVA14: Slow [[VRAM]] bank address bus | ||
*SVD0~SVD15: Slow VRAM bank data bus | *SVD0~SVD15: Slow VRAM bank data bus | ||
*FVA0~FVA10: Fast VRAM bank address bus | *FVA0~FVA10: Fast VRAM bank address bus | ||
*FVD0~FVD15: Fast VRAM bank data bus | *FVD0~FVD15: Fast VRAM bank data bus | ||
[[Category:Chips]] | [[Category:Chips]] | ||
