LSPC-A0: Difference between revisions

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[[File:Mvs_lspc-a0.jpg|right|thumb|LSPC-A0 graphics chip found on a [[MV4]] board.]]
{{ChipInfo
|picture=Mvs_lspc-a0.jpg
|pkg=QFP160
|manu=nec
|date=1990 ?
|gates=
|used_on={{PCB|NEO-AES}} {{PCB|MV1}}
}}


LSPC-A0 is the [[VDC]] part of the first generation chipset, see {{Chipname|LSPC2-A2}} for more details.
LSPC-A0 is the [[VDC]] part of the first generation chipset, see {{Chipname|LSPC2-A2}} for more details.
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*117: 8 ULN2803 K11 / 112 C0
*117: 8 ULN2803 K11 / 112 C0
*116: C0 109
*115: C0 110
*124: 2H1
*125: CA4
*126: F7 LS86 12
*127: C0 37/1 Ls273 E4/5
*127: C0 37/1 Ls273 E4/5
*128: C0 54/B0 21
*128: C0 54/B0 21
*158: 3 D7 (AS04)


[[File:lspc-a0_pinout.png|640px]]
{{Pinout|LSPC-A0|640}}
 
OpenOffice Draw file: [[File:lspc-a0.odg]]


*A1~A3: {{Chipname|68k}} address bus
*A1~A3: {{Chipname|68k}} address bus

Latest revision as of 01:08, 8 July 2018

Package QFP160
Manufacturer
First use 1990 ?
Used on NEO-AES MV1

LSPC-A0 is the VDC part of the first generation chipset, see LSPC2-A2 for more details.

Pinout

  • 117: 8 ULN2803 K11 / 112 C0
  • 127: C0 37/1 Ls273 E4/5
  • 128: C0 54/B0 21


Edit this pinout

  • A1~A3: 68k address bus
  • D0~D15: 68k data bus
  • SVA0~SVA14: Slow VRAM bank address bus
  • SVD0~SVD15: Slow VRAM bank data bus
  • FVA0~FVA10: Fast VRAM bank address bus
  • FVD0~FVD15: Fast VRAM bank data bus
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