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| From [[Link|MAME's source]]:
| | __NOTOC__ |
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| =MVS=
| | Cartridge PCB which holds the [[C ROM|C]] (sprite graphics), [[M1 ROM|M]] (Z80 code) and [[S ROM|S]] (fix graphics) ROMs. |
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| |
|
| ==CHA boards==
| | List from [[https://github.com/mamedev/mame/blob/master/src/mame/drivers/neodriv.hxx MAME's source]]. |
| ===NEO-MVS CHA-32===
| |
| [[File:neo-mvs-cha32.png|x600px]] | |
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| |
|
| ===CHA-8M=== | | =MVS= |
| ===CHA42G===
| |
| ===CHA42G-1===
| |
| ===CHA 42G-2===
| |
| ===CHA 42G-3===
| |
| ===CHA 42G-3B===
| |
| ===CHA256===
| |
| | |
| ====C ROM====
| |
| | |
| Up to 8x 32Mbit ROMs (27C322) can be used for a maximum of 256Mbit C ROM. 27C800/27C160 can also depending on jumper config. Size of largest ROM is selected using a pair of jumpers. The rest should be left unconnected.
| |
| | |
| {| class="wikitable"
| |
| |-
| |
| !ROM size
| |
| !Jumper A
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| !Jumper B
| |
| |-
| |
| |8Mbit
| |
| |J5
| |
| |J6
| |
| |-
| |
| |16Mbit
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| |J7
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| |J8
| |
| |-
| |
| |32Mbit
| |
| |J9
| |
| |J10
| |
| |}
| |
| | |
| ====Pinouts====
| |
| | |
| A NEO-273 and a LS74 is used to address C ROM. LS74 provides the 2 most significant bits. LS139 enables one of four pairs of C ROMs using 2 address inputs depending on which 2 jumpers are connected.
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| {| class="wikitable" | | {| class="wikitable" |
| | !Name |
| | !Chips |
| | !Max C ROM |
| | !Max S ROM |
| | !Max M ROM |
| |- | | |- |
| !Jumper
| | |[[CHA-32]] |
| !LS139
| |
| !LS74
| |
| !NEO-273
| |
| |- | |
| |J5
| |
| |2(1A)
| |
| |N/A
| |
| |45(A19)
| |
| |-
| |
| |J6
| |
| |3(1B)
| |
| |N/A
| |
| |46(A20)
| |
| |-
| |
| |J7
| |
| |2(1A)
| |
| |N/A
| |
| |46(A20)
| |
| |- | | |- |
| |J8 | | |[[CHA-8M]] |
| |3(1B)
| |
| |9(Q2)
| |
| |N/A
| |
| |- | | |- |
| |J9 | | |CHAEP8M (Prototype)||[[NEO-ZMC]],[[NEO-273]]||8*1024||128||128 |
| |2(1A)
| |
| |9(Q2)
| |
| |N/A
| |
| |-
| |
| |J10
| |
| |3(1B)
| |
| |5(Q1) | |
| |N/A | |
| |}
| |
| | |
| *Max 256Mbit C ROM (8x 32Mbit)
| |
| *NEO-273
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| *NEO-ZMC
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| *LS139,LS74
| |
| | |
| ===CHA256B===
| |
| ===CHA512Y===
| |
| *Max 8 8MiB C ROMs
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| *Max 128KiB M1 ROM
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| *Max 128KiB S1 ROM
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| *NEO-273
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| *NEO-ZMC
| |
| *LS139,LS174
| |
| ===CHAFIO===
| |
| *used with NEO-CMC 90G06C7042 or NEO-CMC 90G06C7050
| |
| ===MVS CHAFIO REV1.0 (KOF-2001)===
| |
| ===CHAFIO (SNK 2002)===
| |
| ===CHAFIO===
| |
| *Max 8x 64Mbits (4Mb x 16) C ROMs
| |
| *Max 1x 4Mbits (512Kb x8) M1 ROM
| |
| *used only with NEO-CMC 90G06CF7042 and 90G06C7050
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| | |
| ==PROG boards==
| |
| ===PROG-NAM===
| |
| ===PROG-HERO===
| |
| ===PROG-EP===
| |
| ===PROG-8MB===
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| ===PROG8M42===
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| ===PROG16===
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| ===PROG 42G===
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| ===PROG 42G-COM===
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| ===PROG 42G-1===
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| ===PROG-G2===
| |
| ===PROG 4096===
| |
| ===PROG 4096 B===
| |
| ===PROGGSC===
| |
| ===PROGSM===
| |
| ===PROGSS3===
| |
| ===PROGTOP===
| |
| ===PROGSF1===
| |
| ===PROGEOP===
| |
| ===PROGLBA===
| |
| ===PROGBK1===
| |
| | |
| The only non-protected board that can bankswitch and use all V ROM space. Really common and very useful for homebrew stuff or converts.
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| | |
| ====P ROM====
| |
| | |
| P1 can be 4Mbit, 8Mbit or 16Mbit (27C400/27C800/27C160).
| |
| *If P1 is 16Mbit then some jumper must be set (JB3? didn't look into it. see kof95) and P2 should be empty. First half of P1 is mapped to 0x200000-0x2FFFFF and second half is mapped to 0x000000-0x0FFFFFF.
| |
| *If P1 is 4Mbit or 8Mbit, then P2 can contain a bankswitched ROM (same type as P1 plus 27C322). P1 appears at 0x000000-0x0FFFFF. P2 banked rom appears in 0x200000-0x2FFFFF.
| |
| | |
| ====V ROM====
| |
| | |
| V ROMs can be 8Mbit, 16Mbit or 32Mbit (27C800/27C160/27C322). Size of largest ROM is selected with a pair of jumpers and the other 4 should be left unconnected. 4Mbit can also be used but only if there is one ROM and only in the last used slot.
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| | |
| {| class="wikitable"
| |
| |- | |
| !ROM size
| |
| !Jumper A
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| !Jumper B
| |
| |-
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| |8Mbit
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| |JV1
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| |JV2
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| |-
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| |16Mbit
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| |JV3
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| |JV4
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| |-
| |
| |32Mbit
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| |JV5 | |
| |JV6 | |
| |} | |
| | |
| ====Pinouts====
| |
| | |
| Bankswitching is done with the LS74. It's not needed if the game isn't banked. Any write to an odd 0x200000-0x2FFFFF address will set the bank.
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|
| |
| {| class="wikitable"
| |
| |-
| |
| !Cart edge
| |
| !LS74
| |
| !P2
| |
| |-
| |
| |A5(68k D0)
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| |2(D1)
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| |N/A
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| |-
| |
| |A6(68k D1)
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| |12(D2)
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| |N/A
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| |-
| |
| |A28(PORTWEL)
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| |3(CLK1)
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| |N/A
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| |-
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| |A28(PORTWEL)
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| |11(CLK2)
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| |N/A
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| |-
| |
| |N/A
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| |5(Q1)
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| |42(A19)
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| |-
| |
| |N/A
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| |9(Q2)
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| |32(A20)
| |
| |}
| |
| | |
| One of 4 V ROMs is enabled with a set of LS139 outputs. The pair of V ROM jumpers effectively choose a set of 2 NEO-PCM address outputs to input to the LS139.
| |
| | |
| {| class="wikitable"
| |
| |- | | |- |
| !Jumper
| | |[[CHA256]]||[[NEO-ZMC]],[[NEO-273]]||8*4096||?||? |
| !LS139
| |
| !V ROM
| |
| |- | | |- |
| |JV1 | | |[[CHA256B]]||[[NEO-ZMC]],[[NEO-273]]||8*4096||?||? |
| |2(1A) | |
| |N/A | |
| |- | | |- |
| |JV2 | | |[[CHA42G-1]]||[[NEO-ZMC]],[[NEO-273]]||4*1024||128||128 |
| |3(1B) | |
| |N/A | |
| |- | | |- |
| |JV3 | | |CHA42G-2 |
| |2(1A)
| |
| |N/A
| |
| |- | | |- |
| |JV4 | | |CHA42G-3? |
| |3(1B)
| |
| |N/A
| |
| |- | | |- |
| |JV5 | | |CHA42G-3B |
| |2(1A)
| |
| |N/A
| |
| |- | | |- |
| |JV6 | | |[[CHA512Y]]||[[NEO-ZMC]],[[NEO-273]]||8*8192||128||128 |
| |3(1B) | |
| |N/A | |
| |- | | |- |
| |N/A | | |CHA64-C |
| |4(1Y0) | | |[[NEO-ZMC]] |
| |V1 13(/OE)
| |
| |- | | |- |
| |N/A | | |[[CHAFIO]]||[[NEO-CMC]]42, [[NEO-CMC]]50 |
| |5(1Y1) | |
| |V2 13(/OE) | |
| |- | | |- |
| |N/A | | |CHAMC2||[[NEO-ZMC]],[[NEO-273]]||2*16384||512||512 |
| |6(1Y2) | |
| |V3 13(/OE) | |
| |- | | |- |
| |N/A | | |PSTM-ROMC||-||-||-||- |
| |7(1Y3) | |
| |V4 13(/OE) | |
| |} | | |} |
|
| |
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| The LS08 is used to AND the two PORT /OE signals.
| | ==CHA-32== |
| | [[File:neo-mvs-cha32.png|400px]] |
|
| |
|
| *4x 1/2/4MiB V ROMs
| | ==CHAFIO REV1.0 (KOF-2001)== |
| *1/2MiB P1 ROM
| |
| *1/2/4MiB P2 ROM
| |
| *2x 512KiB EP1/EP2 ROM
| |
| *NEO-PCM
| |
| *LS139,LS08,LS74
| |
|
| |
|
| ===PROGBK2=== | | ==CHAMC2(Prototype Board)== |
| | [[http://www.neogeoprotos.com/games/topsecret2.htm Billy Pit's Neo-Geo Proto Page]] or [[http://www.assemblergames.com/forums/showthread.php?t=23106&page=11]] |
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| Looks identical to PROGBK1 in terms of ROM layout but uses a [[NEO-PCM2]] for encryption plus all other logic that was done with discrete chips on PROGBK1.
| | ==PSTM-ROMC== |
|
| |
|
| ===PROGBK2 REV1.0 (KOF-2001)===
| | The only cart board which hasn't a [[S ROM]]. |
| ===PROGBK2===
| |
| ===PROGBK2R===
| |
| ===PROGBK3R===
| |
| ===PROGBK3S===
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| ===PROGBK2S===
| |
| ===PROGV (Brezzasoft)===
| |
| Same board manufacturer as SNK ?
| |
| *42pin V1 and P1 ROMs (DIP or TSOP)
| |
| *64KiB Battery-backed RAM (Mapped to $200000~?)
| |
| *External I/O port (8 ?)
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| *Room for 2x8DIP switchs
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| [[Category:Chips]] | | [[Category:Chips]] |
| [[Category:Cartridge systems]] | | [[Category:Cartridge systems]] |
| | [[Category:Cartridge boards]] |
