MV2F: Difference between revisions
Jump to navigation
Jump to search
m (i'll get the rest of the info from my board some time) |
mNo edit summary |
||
| Line 5: | Line 5: | ||
todo: formatting, maybe pics | todo: formatting, maybe pics | ||
===C ROM=== | ===C ROM / LSPC2 / NEO-ZMC2=== | ||
todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2? | todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2? | ||
===S ROM=== | ===S ROM / LSPC2 / NEO-B1=== | ||
todo. 16bits of input for FIXD0~FIXD7 to some NEO-257? | todo. 16bits of input for FIXD0~FIXD7 to some NEO-257? | ||
===V ROM=== | ===V ROM / YM2610 access=== | ||
todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses? | todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses? | ||
===P ROM=== | ===P ROM / 68k access=== | ||
todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23? | todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23? | ||
===Z80=== | ===M ROM / Z80 access=== | ||
Z80 A0~A15 is buffered through [[NEO-E0]] @ K10 to SDA0~SDA15 of both cart slots. | Z80 A0~A15 is buffered through [[NEO-E0]] @ K10 to SDA0~SDA15 of both cart slots. | ||
Revision as of 10:13, 5 May 2012
Revised 2 slot board with the second generation chipset.
Pinouts
todo: formatting, maybe pics
C ROM / LSPC2 / NEO-ZMC2
todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?
S ROM / LSPC2 / NEO-B1
todo. 16bits of input for FIXD0~FIXD7 to some NEO-257?
V ROM / YM2610 access
todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses?
P ROM / 68k access
todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?
M ROM / Z80 access
Z80 A0~A15 is buffered through NEO-E0 @ K10 to SDA0~SDA15 of both cart slots.
| Z80 | NEO-E0 |
| A0(30) | A1(64) |
| A1(31) | A2(1) |
| A2(32) | A3(2) |
| A3(33) | A4(3) |
| A4(34) | A5(4) |
| A5(35) | A6(15) |
| A6(36) | A7(16) |
| A7(37) | A8(17) |
| A8(38) | A9(18) |
| A9(39 | A10(19) |
| A10(40) | A11(20) |
| A11(1) | A12(21) |
| A12(2) | A13(31) |
| A13(3) | A14(32) |
| A14(4) | A15(33) |
| A15(5) | A16(34) |
| NEO-E0 | CHA slot #1 & #2 |
| Y0(5) | SDA0(A43) |
| Y1(6) | SDA1(A44) |
| Y2(7) | SDA2(A45) |
| Y3(8) | SDA3(A46) |
| Y4(9) | SDA4(A47) |
| Y5(11) | SDA5(A48) |
| Y6(12) | SDA6(A49) |
| Y7(13) | SDA7(A50) |
| Y8(14) | SDA8(A51) |
| Y9(22) | SDA9(A52) |
| Y10(23) | SDA10(A53) |
| Y11(24) | SDA11(A54) |
| Y12(27) | SDA12(A55) |
| Y13(28) | SDA13(A56) |
| Y14(29) | SDA14(A57) |
| Y15(30) | SDA15(A58) |
Z80 D0~D7 is multiplexed from each slot by NEO-257 @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.
| Z80 | NEO-257 |
| D0(14) | Y8(40) |
| D1(15) | Y9(41) |
| D2(12) | Y10(43) |
| D3(8) | Y11(44) |
| D4(7) | Y12(55) |
| D5(9) | Y13(56) |
| D6(10) | Y14(59) |
| D7(13) | Y15(60) |
| NEO-257 | CHA slot #1 |
| A8(36) | CHA SDD0(B51) |
| A9(38) | CHA SDD1(B52) |
| A10(45) | CHA SDD2(B53) |
| A11(47) | CHA SDD3(B54) |
| A12(51) | CHA SDD4(B55) |
| A13(53) | CHA SDD5(B56) |
| A14(62) | CHA SDD6(B57) |
| A15(64) | CHA SDD7(B58) |
| NEO-257 | CHA slot #2 |
| B8(37) | CHA SDD0(B51) |
| B9(39) | CHA SDD1(B52) |
| B10(46) | CHA SDD2(B53) |
| B11(48) | CHA SDD3(B54) |
| B12(52) | CHA SDD4(B55) |
| B13(54) | CHA SDD5(B56) |
| B14(63) | CHA SDD6(B57) |
| B15(1) | CHA SDD7(B58) |
Multiplexer slot selection from NEO-F0 and /OE from NEO-D0 to NEO-257.
| NEO-D0 | NEO-257 |
| SDROM(11) | Y8~Y15 /OE(33) |
| NEO-F0 | NEO-257 |
| SLOTA(39) | SELECT(17) |
NEO-D0 signals for Z80 reads are also buffered through NEO-E0 @ K10.
| NEO-D0 | NEO-E0 |
| SDMRD(39) | A17(36) |
| SDROM(11) | A18(37) |
| SDRD0(45) | A19(38) |
| SDRD1(46) | A20(48) |
| NEO-E0 | CHA slot #1 & #2 |
| Y16(39) | SDMRD(B50) |
| Y17(40) | SDROM(B49) |
| Y18(41) | SDRD0(B47) |
| Y19(43) | SDRD1(B48) |