VRAM: Difference between revisions
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VRAM | '''VRAM''' stands for Video RAM. | ||
[[File:Aes_cxk5814.jpg|thumb|One of two CXK5814 2KiB RAM chips used for the upper zone of the VRAM ($8000~$87FF) on a AES system]] | [[File:Aes_cxk5814.jpg|thumb|One of two CXK5814 2KiB RAM chips used for the upper zone of the VRAM ($8000~$87FF) on a AES system]] | ||
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The NeoGeo has 68KiB (physically 64KiB + 4KiB, respectively called lower and upper, or slow and fast) of VRAM accessible as 16 bits words, which is used to store [[Sprites|sprite]] attributes, the [[fix layer]] tile map and sprite lists for video rendering. Contrary to other systems, the VRAM here '''does not contain actual graphics'''. | The NeoGeo has 68KiB (physically 64KiB + 4KiB, respectively called lower and upper, or slow and fast) of VRAM accessible as 16 bits words, which is used to store [[Sprites|sprite]] attributes, the [[fix layer]] tile map and sprite lists for video rendering. Contrary to other systems, the VRAM here '''does not contain actual graphics'''. | ||
Access to VRAM is done through 3 [[Memory mapped registers]] handled by the [[GPU]], it isn't mapped in the [[68k]] address space. Every VRAM address points to a word, not a byte. | |||
* {{Reg|REG_VRAMADDR ($3C0000)}} sets the VRAM address for the next read/write operation | * {{Reg|REG_VRAMADDR ($3C0000)}} sets the VRAM address for the next read/write operation | ||
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== Memory map == | == Memory map == | ||
[[File:Vrammap.png|right|frame]] | [[File:Vrammap.png|right|frame]] | ||
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Even if VRAM can be modified at any time (even during active display), since it is not dual-ported, some timing restrictions have to be met in order to avoid skipping writes or reading data too early after setting the address. This is because LSPC allocates a number of "access slots" per video line for the CPU between rendering steps. | Even if VRAM can be modified at any time (even during active display), since it is not dual-ported, some timing restrictions have to be met in order to avoid skipping writes or reading data too early after setting the address. This is because the LSPC allocates a number of "access slots" per video line for the CPU between rendering steps. | ||
== Timing considerations == | == Timing considerations == | ||
The following timings are given to be 100% sure that no read or write to VRAM will fail. It is possible to sometimes shorten them with extreme guessing methods on the CPU side, but it's practically useless. | The following timings are given to be 100% sure that no read or write to VRAM will fail. It is possible to sometimes shorten them with extreme guessing methods on the CPU side, but it's practically useless. | ||
Revision as of 19:59, 10 November 2015
VRAM stands for Video RAM.
The NeoGeo has 68KiB (physically 64KiB + 4KiB, respectively called lower and upper, or slow and fast) of VRAM accessible as 16 bits words, which is used to store sprite attributes, the fix layer tile map and sprite lists for video rendering. Contrary to other systems, the VRAM here does not contain actual graphics.
Access to VRAM is done through 3 Memory mapped registers handled by the GPU, it isn't mapped in the 68k address space. Every VRAM address points to a word, not a byte.
- REG_VRAMADDR ($3C0000) sets the VRAM address for the next read/write operation
- REG_VRAMRW ($3C0002) is the data read or to write
- REG_VRAMMOD ($3C0004) is the signed value added to the VRAM address after a write
The original SNK documentation specifies that the address register should be set directly instead of using REG_VRAMMOD when crossing VRAM zones ($0000~$7FFF to/from $8000~$FFFF). This is probably because the GPU's internal adder is 15 bit only.
Memory map
| Start | End | Description |
| $0000 | $6FFF | SCB1 |
| $7000 | $74FF | Fix map |
| $7500 | $7FFF | Extension |
| $8000 | $81FF | SCB2 |
| $8200 | $83FF | SCB3 |
| $8400 | $85FF | SCB4 |
| $8600 | $867F | Sprite list for even scanlines |
| $8680 | $86FF | Sprite list for odd scanlines |
Even if VRAM can be modified at any time (even during active display), since it is not dual-ported, some timing restrictions have to be met in order to avoid skipping writes or reading data too early after setting the address. This is because the LSPC allocates a number of "access slots" per video line for the CPU between rendering steps.
Timing considerations
The following timings are given to be 100% sure that no read or write to VRAM will fail. It is possible to sometimes shorten them with extreme guessing methods on the CPU side, but it's practically useless.
After a write:
- Another write should be made after at least 12 cycles.
- An address change should be made after at least 16 cycles.
After an address change, reads should be made after at least 16 CPU cycles.
Note that these timings only affect the VRAM access, and not the other LSPC registers.