NEO-273

Package	QFP64R
Manufacturer
First use	1992 ?
Used on	MVS cartridges

The NEO-273 chip is used in cartridges to demultiplex the P bus to C ROM and S ROM addresses (graphics). Ir replaces the discrete 74LS273 and 74LS174 latches that were used in early boards (like CHA-32).

This chip was later superseded by NEO-CMC which performs the same functions along with a lot of other things.

For cartridges that use this chip but have more than 8MiB of sprite graphics data, extra bits were added using discrete chips. An added 74LS74 (2 bits) in CHA256 boards for example increases the C ROM capacity from 8MiB to 32MiB (256Mbits).

Demultiplexing

• The C ROM address is latched on the rising edge of PCK1B.
• The S ROM address is latched on the rising edge of PCK2B.

Mapping of the P bus to the ROM address lines:

P BUS	P19	P18	P17	P16	P15	P14	P13	P12	P11	P10	P9	P8	P7	P6	P5	P4	P3	P2	P1	P0
C address	A3	A2	A1	A0	A20	A19	A18	A17	A16	A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5
S address					A4	A2	A1	A0

Note that A4 (CA4) of the C ROMs and A3 (2H1) of the S ROM are not part of the P bus and come straight from the cartridge edge, bypassing this chip.

P20~23 are left out or routed to additional latches if needed.

An inverted C_A20 signal is available on pin 47 to allow cartridges which use 2MiB C ROMs to switch between 2 pairs without the need for an additional inverter chip.

Internals

It includes one 16-bit latch (to address a 128KiB S ROM) and one 20-bit latch (to address 8MiB of 2*16bits C ROMs).

Pinout

Edit this pinout

Repair

The NEO-273 doesn't appear to fail often. If some outputs are dead, their pins can be lifted and wired to a 74LS74 (2 outputs), a 74LS171 (4 outputs) or 74LS273 (8 outputs).

• Wire the data input to the appropriate P bus line (see table above)
• Wire the output to the address pad
• Wire the clock to either PCK1B or PCK2B depending on the affected address bus.
• Wire power and don't forget to ground the unused inputs if using a CMOS part.