Video DAC: Difference between revisions
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[[File:mvs_viddac.jpg|right|thumb|Resistor array forming the video DAC on a 1FZS.]] | [[File:mvs_viddac.jpg|right|thumb|Resistor array forming the video DAC on a 1FZS.]] | ||
The NeoGeo uses a discrete video DAC made of precision resistors | The NeoGeo uses a discrete video DAC made of precision resistors and two 74LS273 latches which store the color value from the [[palette RAM]] while the pixel has to be displayed. This is controlled by either [[NEO-B1]], [[NEO-GRC]] or [[NEO-GRZ]]. | ||
[[File:aes_viddac.png|right|thumb|Video DAC on a AES board.]] | [[File:aes_viddac.png|right|thumb|Video DAC on a AES board.]] | ||
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[[File:aes_viddac_schematic.png]] | [[File:aes_viddac_schematic.png]] | ||
Each color component has its own set of 7 resistors. 6 of them are used with the actual color value | Each color component has its own set of 7 resistors. 6 of them are used with the actual color value (5 + 1 [[Palettes|common bit]]). The last (SHADOW signal) is related to the '''REG_SHADOW''' and '''REG_NOSHADOW''' registers (74HC259 latch). | ||
The output voltage is then divided by 5 to obtain a 1Vp-p max signal, which can be fed to the [[CXA1145]] encoder. | The output voltage is then divided by 5 to obtain a 1Vp-p max signal, which can be fed to the [[CXA1145]] encoder. | ||
Revision as of 14:03, 11 October 2011
The NeoGeo uses a discrete video DAC made of precision resistors and two 74LS273 latches which store the color value from the palette RAM while the pixel has to be displayed. This is controlled by either NEO-B1, NEO-GRC or NEO-GRZ.
Each color component has its own set of 7 resistors. 6 of them are used with the actual color value (5 + 1 common bit). The last (SHADOW signal) is related to the REG_SHADOW and REG_NOSHADOW registers (74HC259 latch).
The output voltage is then divided by 5 to obtain a 1Vp-p max signal, which can be fed to the CXA1145 encoder.