|First use||1992 ?|
|Used on||NEO-AES3-4 board...|
The NEO-B1 chip is found in second generation cartridge-based systems.
Both fix graphics from the S ROM and serialized sprite graphics from the C ROMs are fed to NEO-B1 for display on screen via 2 pairs of alternating line buffers. Sprite graphics come from the C ROM multiplexer ( NEO-ZMC2, PRO-CT0 or NEO-CMC), while fix graphics come directly from the currently enabled fix ROM. Two pixels are written at a time.
Sprite rendering is done in the internal line buffers.
The chip outputs the palette RAM address to select colors for pixel output. The data output of the palette RAM is latched by a pair of 8bit registers, which in turn feed the video DAC. The NEO-B1 handles address bus switching between the 68k bus and palette RAM. Priority is always given to the 68k which results in harmless display glitches when games access palette RAM during active display.
The watchdog is integrated into NEO-B1. HALT and RESET are generated by this chip on power-on and whenever the 68k fails to kick the watchdog in time. The write to REG_DIPSW is decoded on the chip instead of using a signal from NEO-C1.
Watchdog can be disabled by bringing pin 94 DOGE to ground (J2 jumper on main board).
OpenOffice Draw file: File:Neo-b1.odg
- A1~A21: 68k address bus
- A22I,A23I: 68k A22,A23 passed through NEO-E0
- FIX0~FIX7: Fix ROM data bus
- PCK1/PCK2: Latch signals, shared with LSPC2-A2 (inverted for NEO-273)
- PA0~PA11: Palette RAM address bus
- TDO0~TDO11: NC on the MV1F
- GAD0~GAD3, GBD0~GBD3: Sprite pixel data (2 pixels)
- FLIP: Flip display horizontally ? Always tied to ground.
- WE1~WE4: Write enable for sprite pixels
- CK1~CK4: Stepping clocks
- SS1/SS2: ?
- LD1/LD2: Odd/Even scanline load ? Changes according to sprite list ?
- TMS0: Line buffer selection
- DOGE: Watchdog enable (internal pullup)