MV2F

Revised 2 slot board with the second generation chipset.

Pinouts

todo: formatting, maybe pics

C ROM / LSPC2 / NEO-ZMC2

todo. Pair of NEO-257 on far left of board used for this? 32 bits per slot multiplexed to NEO-ZMC2?

S ROM / LSPC2 / NEO-B1

FIXD0~FIXD7 is multiplexed from each from by NEO-257 @ J9. Same one is used for Z80 D0~D7 for cart M1 access.

NEO-257	CHA slot #1
A0(4)	FIXD0(B39)
A1(6)	FIXD1(B40)
A2(13)	FIXD2(B41)
A3(15)	FIXD3(B42)
A4(19)	FIXD4(B43)
A5(21)	FIXD5(B44)
A6(29)	FIXD6(B45)
A7(31)	FIXD7(B46)

NEO-257	CHA slot #2
B0(5)	FIXD0(B39)
B1(7)	FIXD1(B40)
B2(14)	FIXD2(B41)
B3(16)	FIXD3(B42)
B4(20)	FIXD4(B43)
B5(22)	FIXD5(B44)
B6(30)	FIXD6(B45)
B7(32)	FIXD7(B46)

Selected FIX data is output to NEO-B1 from Y0~Y7.

NEO-257	NEO-B1
Y0(8)	FIXD0(131)
Y1(9)	FIXD1(132)
Y2(11)	FIXD2(133)
Y3(12)	FIXD3(134)
Y4(23)	FIXD4(135)
Y5(24)	FIXD5(136)
Y6(27)	FIXD6(137)
Y7(28)	FIXD7(138)

The 257 seems to have common enable/select lines. See M ROM section for those as cart M ROM/S ROM are always enabled together.

V ROM / YM2610 access

todo. NEO-E0 for address outputs only, some NEO-G0 for the databuses?

ADPCM-A

YM2610 RAD0~RAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins. (NEO-G0 needs a proper set of pin names).

NEO-G0	YM2610
(2)	RAD0(17)
(3)	RAD1(16)
(4)	RAD2(15)
(5)	RAD3(14)
(15)	RAD4(13)
(16)	RAD5(12)
(17)	RAD6(11)
(18)	RAD7(10)

NEO-G0	PROG slot #1
(6)	SDRAD0(B49)
(7)	SDRAD1(B50)
(8)	SDRAD2(B51)
(9)	SDRAD3(B52)
(11)	SDRAD4(B53)
(12)	SDRAD5(B54)
(13)	SDRAD6(B55)
(14)	SDRAD7(B56)

NEO-G0	PROG slot #2
(62)	SDRAD0(B49)
(63)	SDRAD1(B50)
(64)	SDRAD2(B51)
(1)	SDRAD3(B52)
(21)	SDRAD4(B53)
(22)	SDRAD5(B54)
(23)	SDRAD6(B55)
(24)	SDRAD7(B56)

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

NEO-E0	YM2610
A7(16)	RA8(23)
A8(17)	RA9(22)
A9(18)	RA20(35)
A10(19)	RA21(36)
A11(20)	RA22(37)
A12(21)	RA23(38)
A13(31)	RMPX(20)
A14(32)	/ROE(21)

NEO-E0	PROG slot #1 & #2
Y6(12)	SDRA8(A49)
Y7(13)	SDRA9(A50)
Y8(14)	SDRA20(A51)
Y9(22)	SDRA21(A52)
Y10(23)	SDRA22(A53)
Y11(24)	SDRA23(A54)
Y12(27)	SDRMPX(A55)
Y13(28)	SDROE(A56)

Direction control of NEO-G0 (D0~D7) @ K9 is set to inverted /ROE from YM2610.

NEO-E0	74AS04
Y13(28)	A5(11)

NEO-G0	74AS04
D0~D7 dir(40)	Y5(10)

ADPCM-B

YM2610 PAD0~PAD7 goes through NEO-G0 @ K9 and out to each cart slot through a separate set of pins.

NEO-G0	YM2610
(31)	PAD0(48)
(32)	PAD1(49)
(33)	PAD2(50)
(34)	PAD3(51)
(47)	PAD4(52)
(48)	PAD5(53)
(49)	PAD6(54)
(50)	PAD7(55)

NEO-G0	PROG slot #1
(27)	SDPAD0(B41)
(28)	SDPAD1(B42)
(29)	SDPAD2(B43)
(30)	SDPAD3(B44)
(43)	SDPAD4(B45)
(44)	SDPAD5(B46)
(45)	SDPAD6(B47)
(46)	SDPAD7(B48)

NEO-G0	PROG slot #2
(35)	SDPAD0(B41)
(36)	SDPAD1(B42)
(37)	SDPAD2(B43)
(38)	SDPAD3(B44)
(53)	SDPAD4(B45)
(54)	SDPAD5(B46)
(55)	SDPAD6(B47)
(56)	SDPAD7(B48)

Control signals and other address lines buffered through NEO-E0 to both cart slots @ F8.

NEO-E0	YM2610
A15(33)	PA8(41)
A16(34)	PA9(42)
A17(36)	PA10(43)
A18(37)	PA11(44)
A19(38)	PMPX(47)
A20(48)	/POE(46)

NEO-E0	PROG slot #1 & #2
Y14(29)	SDPA8(A43)
Y15(30)	SDPA9(A44)
Y16(39)	SDPA10(A45)
Y17(40)	SDPA11(A46)
Y18(41)	SDPMPX(A47)
Y19(43)	SDPOE(A48)

Direction control of NEO-G0 (D8~D15) @ K9 is set to inverted /POE from YM2610.

NEO-E0	74AS04
Y19(43)	A6(13)

NEO-G0	74AS04
D8~D15 dir(52)	Y6(12)

P ROM / 68k access

todo. some NEO-G0 for D0~D15? NEO-E0 for A1~A23?

M ROM / Z80 access

Z80 A0~A15 is buffered through NEO-E0 @ K10 to SDA0~SDA15 of both cart slots.

Z80	NEO-E0
A0(30)	A1(64)
A1(31)	A2(1)
A2(32)	A3(2)
A3(33)	A4(3)
A4(34)	A5(4)
A5(35)	A6(15)
A6(36)	A7(16)
A7(37)	A8(17)
A8(38)	A9(18)
A9(39	A10(19)
A10(40)	A11(20)
A11(1)	A12(21)
A12(2)	A13(31)
A13(3)	A14(32)
A14(4)	A15(33)
A15(5)	A16(34)

NEO-E0	CHA slot #1 & #2
Y0(5)	SDA0(A43)
Y1(6)	SDA1(A44)
Y2(7)	SDA2(A45)
Y3(8)	SDA3(A46)
Y4(9)	SDA4(A47)
Y5(11)	SDA5(A48)
Y6(12)	SDA6(A49)
Y7(13)	SDA7(A50)
Y8(14)	SDA8(A51)
Y9(22)	SDA9(A52)
Y10(23)	SDA10(A53)
Y11(24)	SDA11(A54)
Y12(27)	SDA12(A55)
Y13(28)	SDA13(A56)
Y14(29)	SDA14(A57)
Y15(30)	SDA15(A58)

Z80 D0~D7 is multiplexed from each slot by NEO-257 @ J9. No need for bidirectional D0~D7 since only reads can be done from cart.

Z80	NEO-257
D0(14)	Y8(40)
D1(15)	Y9(41)
D2(12)	Y10(43)
D3(8)	Y11(44)
D4(7)	Y12(55)
D5(9)	Y13(56)
D6(10)	Y14(59)
D7(13)	Y15(60)

NEO-257	CHA slot #1
A8(36)	CHA SDD0(B51)
A9(38)	CHA SDD1(B52)
A10(45)	CHA SDD2(B53)
A11(47)	CHA SDD3(B54)
A12(51)	CHA SDD4(B55)
A13(53)	CHA SDD5(B56)
A14(62)	CHA SDD6(B57)
A15(64)	CHA SDD7(B58)

NEO-257	CHA slot #2
B8(37)	CHA SDD0(B51)
B9(39)	CHA SDD1(B52)
B10(46)	CHA SDD2(B53)
B11(48)	CHA SDD3(B54)
B12(52)	CHA SDD4(B55)
B13(54)	CHA SDD5(B56)
B14(63)	CHA SDD6(B57)
B15(1)	CHA SDD7(B58)

Multiplexer slot selection from NEO-F0, /OE from NEO-D0 and OE from 74HC259 to NEO-257. The 257 must only output to Z80 when it is trying to read ROM (NEO-D0) and the cart M1/S1 is selected (74HC259).

NEO-D0	NEO-257
SDROM(11)	Y8~Y15 /OE(33)

NEO-F0	NEO-257
SLOTA(39)	SELECT(17)

74HC259	NEO-257
Q5(10)	Y8~Y15 OE(35)

NEO-D0 signals for Z80 reads are also buffered through NEO-E0 @ K10.

NEO-D0	NEO-E0
SDMRD(39)	A17(36)
SDROM(11)	A18(37)
SDRD0(45)	A19(38)
SDRD1(46)	A20(48)

NEO-E0	CHA slot #1 & #2
Y16(39)	SDMRD(B50)
Y17(40)	SDROM(B49)
Y18(41)	SDRD0(B47)
Y19(43)	SDRD1(B48)