Signals: Difference between revisions
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*/PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access | */PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access | ||
*CR0~CR31: [[C ROM]]s data bus (2*16bits), holds data for one 8 pixels line | *CR0~CR31: [[C ROM]]s data bus (2*16bits), holds data for one 8 pixels line | ||
*SDA0~SDA15 : [[Z80]] address bus | |||
*SDD0~SDD7: Z80 data bus | |||
*SDRAD0~SDRAD7: ADPCM-A ROM [[YM2610#Multiplexed bus|multiplexed bus]] (data/address) | *SDRAD0~SDRAD7: ADPCM-A ROM [[YM2610#Multiplexed bus|multiplexed bus]] (data/address) | ||
*SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus | *SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus | ||
*SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address) | *SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address) | ||
*SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus | *SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus | ||
*P0~P23: C ROM, [[S ROM]] and [[LO ROM]] address bus (multiplexed) | *P0~P23: C ROM, [[S ROM]] and [[LO ROM]] address/data bus (multiplexed) | ||
*PCK1B: Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge | *PCK1B: Clock to latch C ROM address from P0~P23 ([[NEO-273|mapping]]) on rising edge | ||
*PCK2B: Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge | *PCK2B: Clock to latch S ROM address from P0~P15 ([[NEO-273|mapping]]) on rising edge | ||
Revision as of 22:57, 3 July 2012
- 6M, 12M, 24M: 6MHz, 12MHz, and 24MHz clock signals
- 4MB: 4MHz inverted signal
- A1~A19: 68k address bus
- D0~D15: 68k data bus
- R/W: 68k Read/Write
- AS: 68k /AS
- /ROMOEL: $000000-$0FFFFF (P1 ROM) odd byte read
- /ROMOEU: $000000-$0FFFFF (P1 ROM) even byte read
- /ROMOE: $000000-$0FFFFF (P1 ROM) read
- /PORTOEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte read
- /PORTOEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte read
- /PORTWEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte write
- /PORTWEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte write
- /PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access
- CR0~CR31: C ROMs data bus (2*16bits), holds data for one 8 pixels line
- SDA0~SDA15 : Z80 address bus
- SDD0~SDD7: Z80 data bus
- SDRAD0~SDRAD7: ADPCM-A ROM multiplexed bus (data/address)
- SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
- SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
- SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
- P0~P23: C ROM, S ROM and LO ROM address/data bus (multiplexed)
- PCK1B: Clock to latch C ROM address from P0~P23 (mapping) on rising edge
- PCK2B: Clock to latch S ROM address from P0~P15 (mapping) on rising edge
- CA4: C ROM A4
- 2H1: S ROM A3
- FIXD0~FIXD7: S ROM data bus