NEO-E0: Difference between revisions
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MVS specific chip. | MVS specific chip. | ||
== | ==System ROM vector table swapping== | ||
When 68k A8~A23 = 0 and the [[ | When 68k A8~A23 = 0 and the [[System ROM]]'s vector table is chosen (by using {{Reg|REG_SWPBIOS}} or {{Reg|REG_SWPROM}}), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a system ROM access instead of a [[P ROM]] access. | ||
[[User:Kyuusaku]]: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}} | [[User:Kyuusaku]]: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}} | ||
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*MCA0~MCA23: [[memory card]] address bus | *MCA0~MCA23: [[memory card]] address bus | ||
*BNK0~BNK2: memory card banking from [[NEO-D0]] | *BNK0~BNK2: memory card banking from [[NEO-D0]] | ||
*VEC: [[ | *VEC: [[System ROM]] vector table swapping enable | ||
|} | |} | ||
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*Y0~Y23: memory card address bus | *Y0~Y23: memory card address bus | ||
*BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] banking | *BNK0~BNK2: comes from [[NEO-D0]], [[memory card]] banking | ||
*VEC: | *VEC: System ROM vector table swapping enable | ||
*ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL | *ANI0, ANI1, AND0: AND gate used to generate ROMOE from ROMOEU and ROMOEL | ||
|} | |} | ||
[[Category:Chips]] | [[Category:Chips]] | ||
Revision as of 06:40, 28 October 2015
MVS specific chip.
System ROM vector table swapping
When 68k A8~A23 = 0 and the System ROM's vector table is chosen (by using REG_SWPBIOS or REG_SWPROM), A22I~A23I outputs are set to 1. This makes the address appear to address decoding chips as a system ROM access instead of a P ROM access.
User:Kyuusaku: {A23Z,A22Z} = A[23:22] ^ 2{~|{A[21:7],^A[23:22],VEC}}
On the AES, the AND gate is used for /SROMOE from /SROMOEL AND /SROMOEU.
MV2B @ H7 pinout
55 = sPCK1B 56 = sPCK2B
MV2B @ G2 pinout
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OpenOffice Draw file: File:Neo-e0 mv2b G2.odg |
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MV2B @ F7 pinout
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OpenOffice Draw file: File:Neo-e0 mv2b F7.odg |
Acts just as a buffer.
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Pinout
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OpenOffice Draw file: File:Neo-e0.odg |
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