YM2610 registers

SSG part

File:Ym2610egshapes.png

Selectable EG shapes of the SSG

Address (Z80 port 4)	Data (Z80 port 5)
$00	Bit 7 6 5 4 3 2 1 0 Def Fine tune	Channel A
$01	Bit 7 6 5 4 3 2 1 0 Def - Coarse tune
$02	Bit 7 6 5 4 3 2 1 0 Def Fine tune	Channel B
$03	Bit 7 6 5 4 3 2 1 0 Def - Coarse tune
$04	Bit 7 6 5 4 3 2 1 0 Def Fine tune	Channel C
$05	Bit 7 6 5 4 3 2 1 0 Def - Coarse tune
$06	Bit 7 6 5 4 3 2 1 0 Def - Noise tune	Noise channel
$07	Bit 7 6 5 4 3 2 1 0 Def - /EN noise C /EN noise B /EN noise A /EN C /EN B /EN A	/Enable for Noise and Tone
$08	Bit 7 6 5 4 3 2 1 0 Def - Mode Volume	Channel A
$09	Bit 7 6 5 4 3 2 1 0 Def - Mode Volume	Channel B
$0A	Bit 7 6 5 4 3 2 1 0 Def - Mode Volume	Channel C
$0B	Bit 7 6 5 4 3 2 1 0 Def Volume envelope period fine tune
$0C	Bit 7 6 5 4 3 2 1 0 Def Volume envelope period coarse tune
$0D	Bit 7 6 5 4 3 2 1 0 Def - Volume envelop shape	See diagram.

If 'Mode' = 1, the EG is used instead of the 4bit volume value. f = 8M / (Coarse*256 + Fine) ?

Timers

Address (Z80 port 4)	Data (Z80 port 5)
$24	Bit 7 6 5 4 3 2 1 0 Def TA counter load bits 9-2
$25	Bit 7 6 5 4 3 2 1 0 Def - TA counter load bits 1-0
$26	Bit 7 6 5 4 3 2 1 0 Def TB counter load bits 0-7
$27	Bit 7 6 5 4 3 2 1 0 Def CSM Mode 3 slot mode Reset TB flag Reset TA flag Enable TB IRQ Enable TA IRQ Load TB Load TA

• TA = Timer A, TB = Timer B
• Timers will tick until they have reached zero, at which point an IRQ will be generated if enabled. Reading port $04 will show which timer caused it.
• The actual timer counter registers are not directly accessable. They can be reset to zero or initialised from load registers $24-$26
  • Writing 0 to the load bits in register $27 will reset the timer counter registers to zero
  • Writing 1 to the load bits will copy the respective timer load register to the timer counter. This only works when the timer is at zero.
• When a timer expires, it is automatically reloaded from the load registers and continues.
• Timer flag reset refers to the same flags that are read from port $04
• CSM mode is for automatic key on for operators on the second FM channel when timer A expires?

FM part

Common FM Registers

Address (Z80 port 4)	Data (Z80 port 5)
$22	Bit 7 6 5 4 3 2 1 0 Def - On Control	LFO Frequency
$28	Bit 7 6 5 4 3 2 1 0 Def Slot - Channel	Key On/Off

LFO Frequency values are as follows:

• 0 – 3.98
• 1 – 5.56
• 2 – 6.02
• 3 – 6.37
• 4 – 6.88
• 5 – 9.63
• 6 – 48.1
• 7 – 72.2

Channel Registers

Depending on which channel you want to write to, the ports used are different:

• Channels 1/2: Ports 4/5
• Channels 3/4: Ports 6/7

Per-Operator Registers

The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

Operator	1	2	3	4
Channels 1, 3	$x1	$x5	$x9	$xD
Channels 2, 4	$x2	$x6	$xA	$xE

Address (Z80 port 4 or 6)	Data (Z80 port 5 or 7)
$31-$3E	Bit 7 6 5 4 3 2 1 0 Def - DT MUL	Detune (DT) and Multiple (MUL)
$41-$4E	Bit 7 6 5 4 3 2 1 0 Def - Total Level	Total Level (Volume)
$51-$5E	Bit 7 6 5 4 3 2 1 0 Def KS - AR	Key Scale (KS) and Attack Rate (AR)
$61-$6E	Bit 7 6 5 4 3 2 1 0 Def AM - DR	AM On (AM) and Decay Rate (DR)
$71-$7E	Bit 7 6 5 4 3 2 1 0 Def - SR	Sustain Rate (SR)
$81-$8E	Bit 7 6 5 4 3 2 1 0 Def SL RR	Sustain Level (SL) and Release Rate (RR)
$91-$9E	Bit 7 6 5 4 3 2 1 0 Def - SSG-EG	SSG-EG

Overall Channel Registers

The first value listed in the Address column is for channels 1/3; the second is for channels 2/4.

Address (Z80 port 4 or 6)	Data (Z80 port 5 or 7)
$A1,$A2	Bit 7 6 5 4 3 2 1 0 Def F-Num 1	F-Numbers and Block (1/2)
$A5,$A6	Bit 7 6 5 4 3 2 1 0 Def - Block F-Num 2	F-Numbers and Block (2/2) (must set this first)
$A9,$AA	Bit 7 6 5 4 3 2 1 0 Def 2CH * F-Num 1	2CH - 2 Slot F-Numbers/Block (1/2)
$AD,$AE	Bit 7 6 5 4 3 2 1 0 Def - 2CH * Block 2CH * F-Num 2	2CH - 2 Slot F-Numbers/Block (1/2) (must set this first)
$B1,$B2	Bit 7 6 5 4 3 2 1 0 Def - FB ALGO	Feedback (FB) and Algorithm (ALGO)
$B5,B6	Bit 7 6 5 4 3 2 1 0 Def L R AMS - PMS	Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)

ADPCM-A part

'Dump' in register $00 is the key on/off bit. Write 0 to start playing specified channels and write 1 to stop playing.

Address (Z80 port 6)	Data (Z80 port 7)
$00	Bit 7 6 5 4 3 2 1 0 Def Dump - CH6 ON CH5 ON CH4 ON CH3 ON CH2 ON CH1 ON
$01	Bit 7 6 5 4 3 2 1 0 Def - Master volume
$08~$0D (one for each channel)	Bit 7 6 5 4 3 2 1 0 Def L R - Channel volume
$10~$15 (one for each channel)	Bit 7 6 5 4 3 2 1 0 Def Sample's start address/256 LSB
$18~$1D (one for each channel)	Bit 7 6 5 4 3 2 1 0 Def Sample's start address/256 MSB
$20~$25 (one for each channel)	Bit 7 6 5 4 3 2 1 0 Def Sample's stop address/256 LSB
$28~$2D (one for each channel)	Bit 7 6 5 4 3 2 1 0 Def Sample's stop address/256 MSB

ADPCM-B part

Address (Z80 port 4)	Data (Z80 port 5)
$10	Bit 7 6 5 4 3 2 1 0 Def Start - Repeat - Reset	Start/Repeat/Reset flags
$11	Bit 7 6 5 4 3 2 1 0 Def L R -	Left/Right Output
$12	Bit 7 6 5 4 3 2 1 0 Def Sample's start address/256 LSB
$13	Bit 7 6 5 4 3 2 1 0 Def Sample's start address/256 MSB
$14	Bit 7 6 5 4 3 2 1 0 Def Sample's stop address/256 LSB
$15	Bit 7 6 5 4 3 2 1 0 Def Sample's stop address/256 MSB
$19	Bit 7 6 5 4 3 2 1 0 Def Delta-N (L)	Determines sample playback rate
$1A	Bit 7 6 5 4 3 2 1 0 Def Delta-N (H)
$1B	Bit 7 6 5 4 3 2 1 0 Def ADPCM-B channel volume
$1C	Bit 7 6 5 4 3 2 1 0 Def B - A6 A5 A4 A3 A2 A1	ADPCM-A & B channels flag control

• Datasheet states playback formula as F=[Delta-N / 256] x 55.5KHz (correct?)
• Write to flag control to reset/mask channel end flags
  • Write 1 to reset and/or mask selected flag
  • Write 0 to unmask selected flag
  • Masking a flag will prevent it from being raised when a channel sample reach its end, this means you have to write 1, then 0 to clear a flag and keep it active.
  • Flags must be manually cleared, playing a new sample on the channel won't clear it.

Reading

The only writable registers that can also be read are from the SSG. All other ports and addresses return different data.

Z80 port #	Data	Notes
$04	Bit 7 6 5 4 3 2 1 0 Def Busy - Timer B flag Timer A flag	When a timer expires and IRQ is enabled for the timer, the respective bit is set
$05	Bit 7 6 5 4 3 2 1 0 Def SSG register data	Attempting to read non-SSG registers will fail
$06	Bit 7 6 5 4 3 2 1 0 Def ADPCM-B end - CH6 end CH5 end CH4 end CH3 end CH2 end CH1 end	When a channel has reached the end address and stops, the respective bit is set, unless masked
$07	not implemented	Always returns $00