Signals: Difference between revisions

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=Clocks=
{| class="regdef"
{| class="regdef"
|'''Name'''
|'''Name'''
|'''Description'''
|'''Description'''
|'''Type'''
|'''Type'''
|'''Polarity'''
|'''Comes from'''
|'''Comes from'''
|'''Fault consequence'''
|'''Fault consequence'''
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|24MHz master clock
|24MHz master clock
|Clock
|Clock
|
|{{Chipname|NEO-D0}}
|{{Chipname|NEO-D0}}
|Nothing works
|Nothing works, no video at all
|-
|-
|12M
|12M
|12MHz clock (24/2) non-inverted
|12MHz clock (24/2) non-inverted
|Clock
|Clock
|
|{{Chipname|NEO-D0}}
|{{Chipname|NEO-D0}}
|Bad graphics
|Bad graphics
|-
|8M
|8MHz clock (24/3) non-inverted
|Clock
|{{Chipname|LSPC}}
|No sound
|-
|6MB
|6MHz clock (24/4) inverted
|Clock
|{{Chipname|NEO-D0}}
|Black screen ?
|-
|4M
|4MHz clock (24/6) non-inverted
|Clock
|{{Chipname|LSPC}}
|No sound
|-
|4MB
|4MHz clock (24/6) inverted
|Clock
|?
|?
|-
|1MB
|'''3MHz''' (!) clock (24/8) inverted
|Clock
|{{Chipname|NEO-D0}}
|?
|-
|68KCLK
|12MHz clock (24/2) non-inverted
|Clock
|{{Chipname|NEO-D0}}
|[[Click of death]]
|-
|68KCLKB
|12MHz clock (24/2) inverted
|Clock
|{{Chipname|NEO-D0}}
|?
|-
|2H1
|[[S ROM]] A3
|Address
|{{Chipname|LSPC}}
|Bad fix graphics
|-
|A1~A23
|[[68k]] address bus
|Address
|{{Chipname|68k}}
|Click of death
|-
|A22I,A23I
|Altered address lines for [[68k vector table]] swap
|Address
|?
|Probably click of death
|-
|AS
|68k Address Strobe
|Control
|{{Chipname|68k}}
|Probably click of death
|-
|BNK0~2
|[[Memory card]] bank selection
|Control
|?
|Errors on access to big memory cards
|-
|CA4
|[[C ROM]]s A4
|Address
|{{Chipname|LSPC}}
|Bad sprite graphics
|-
|C* or CR0~CR31
|C ROMs data bus (2*16bits), data for one 8-pixels line
|Data
|{{Chipname|C ROM}}
|Bad sprite graphics
|-
|D0~D15
|68k data bus
|Data
|Multiple
|Click of death
|}
|}


*8M: 8MHz clock (24/3) non-inverted from LSPC
*6MB: 6MHz clock (24/4) inverted from NEO-D0
*4M: 4MHz clock (24/6) non-inverted from LSPC
*4MB: 4MHz clock (24/6) inverted from LSPC+AS04
*1MB: 3MHz clock (24/8) inverted from NEO-D0
*68KCLK: 12MHz clock (24/2) non-inverted from NEO-D0 (always equivalent to 12M ?)
*68KCLKB: 12MHz clock (24/2) inverted from NEO-D0
*2H1: [[S ROM]] A3
*A1~A23: [[68k]] address bus
*A22I,A23I: A22 and A23 modified for [[68k vector table]] swap
*AS: 68k Address Strobe
*BNK0~2: [[Memory card]] bank selection
*CA4: [[C ROM]]s A4
*C* or CR0~CR31: C ROMs data bus (2*16bits), holds data for one 8-pixels line
*D0~D15: 68k data bus
*/DTACK: 68k Data Transmit ACKnowledge, used to slow down acces to memory (see [[wait cycles]])
*/DTACK: 68k Data Transmit ACKnowledge, used to slow down acces to memory (see [[wait cycles]])
*FIXD0~FIXD7: Fix layer data bus, holds data for 2 pixels
*FIXD0~FIXD7: Fix layer data bus, holds data for 2 pixels

Revision as of 11:23, 2 February 2016

Clocks

Name Description Type Comes from Fault consequence
24M 24MHz master clock Clock NEO-D0 Nothing works, no video at all
12M 12MHz clock (24/2) non-inverted Clock NEO-D0 Bad graphics
8M 8MHz clock (24/3) non-inverted Clock LSPC No sound
6MB 6MHz clock (24/4) inverted Clock NEO-D0 Black screen ?
4M 4MHz clock (24/6) non-inverted Clock LSPC No sound
4MB 4MHz clock (24/6) inverted Clock ? ?
1MB 3MHz (!) clock (24/8) inverted Clock NEO-D0 ?
68KCLK 12MHz clock (24/2) non-inverted Clock NEO-D0 Click of death
68KCLKB 12MHz clock (24/2) inverted Clock NEO-D0 ?
2H1 S ROM A3 Address LSPC Bad fix graphics
A1~A23 68k address bus Address 68k Click of death
A22I,A23I Altered address lines for 68k vector table swap Address ? Probably click of death
AS 68k Address Strobe Control 68k Probably click of death
BNK0~2 Memory card bank selection Control ? Errors on access to big memory cards
CA4 C ROMs A4 Address LSPC Bad sprite graphics
C* or CR0~CR31 C ROMs data bus (2*16bits), data for one 8-pixels line Data C ROM Bad sprite graphics
D0~D15 68k data bus Data Multiple Click of death
  • /DTACK: 68k Data Transmit ACKnowledge, used to slow down acces to memory (see wait cycles)
  • FIXD0~FIXD7: Fix layer data bus, holds data for 2 pixels
  • P0~P23: C ROM, S ROM, LO ROM and internal address/data bus (multiplexed P bus)
  • PA0~PA11: Palette RAM address bus
  • PAL: Palette RAM address decode for 68k access
  • PCK1B: Low 55ns, high 610 (1.5MHz) Clock to latch C ROM address from P0~P23 (mapping) on rising edge.
  • PCK2B: Low 55ns, high 610 (1.5MHz) Clock to latch S ROM address from P0~P15 (mapping) on rising edge.
  • /PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access
  • /PORTOEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte read
  • /PORTOEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte read
  • /PORTWEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte write
  • /PORTWEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte write
  • /PWAIT0, /PWAIT1: adds 0 to 3 cycle delay for P2 ROM reads, see wait cycles
  • R/W: 68k Read/Write
  • /ROMOE: $000000-$0FFFFF (P1 ROM) read
  • /ROMOEL: $000000-$0FFFFF (P1 ROM) odd byte read
  • /ROMOEU: $000000-$0FFFFF (P1 ROM) even byte read
  • /ROMWAIT: add 1-cycle delay for P1 ROM reads
  • /SROMOE: $C00000-$CFFFFF (System ROM) read
  • /SROMOEL: $C00000-$CFFFFF (System ROM) odd byte read
  • /SROMOEU: $C00000-$CFFFFF (System ROM) even byte read
  • SDA0~SDA15 : Z80 address bus
  • SDD0~SDD7: Z80 data bus
  • SDRAD0~SDRAD7: ADPCM-A ROM multiplexed bus (data/address)
  • SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
  • SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
  • SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
  • SYSTEM: low when onboard ROMs selected
  • SYSTEMB: inverted SYSTEM
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