Revision as of 05:29, 6 April 2016

Most names come from the official schematics.

Clocks

Name	Description	Type	Comes from	Fault consequence
24M	24MHz master clock	Clock	NEO-D0	Nothing works, no video at all
12M	12MHz clock (24/2) non-inverted	Clock	NEO-D0	Bad graphics
8M	8MHz clock (24/3) non-inverted	Clock	LSPC	No sound
6MB	6MHz clock (24/4) inverted	Clock	NEO-D0	Black screen ?
4M	4MHz clock (24/6) non-inverted	Clock	LSPC	No sound
4MB	4MHz clock (24/6) inverted	Clock	?	?
1MB	3MHz (!) clock (24/8) inverted	Clock	NEO-D0	?
68KCLK	12MHz clock (24/2) non-inverted	Clock	NEO-D0	Click of death
68KCLKB	12MHz clock (24/2) inverted	Clock	NEO-D0	?
2H1	S ROM A3	Address	LSPC	Bad fix graphics
A1~A23	68k address bus	Address	68k	Click of death
A22I,A23I	Altered address lines for 68k vector table swap	Address	?	Probably click of death
AS	68k Address Strobe	Control	68k	Probably click of death
BNK0~2	Memory card bank selection	Control	?	Errors on access to big memory cards
CA4	C ROMs A4	Address	LSPC	Bad sprite graphics
C* or CR0~CR31	C ROMs data bus (2*16bits), data for one 8-pixels line	Data	C ROM	Bad sprite graphics
D0~D15	68k data bus	Data	Multiple	Click of death
/DTACK	68k Data Transmit ACKnowledge (see wait cycles)	Control	68k	Click of death ?
FIXD0~FIXD7	Fix layer data bus, data for 2 pixels	Data	S ROM	Garbled graphics, solid color screen
P0~P23	Multiplexed P bus	Muxed	Multiple	Garbled or absent graphics
PA0~PA11	Palette RAM address bus	Address	NEO-B1	Bad colors, snow, black screen

PAL: Palette RAM address decode for 68k access
PCK1B: Low 55ns, high 610 (1.5MHz) Clock to latch C ROM address from P0~P23 (mapping) on rising edge.
PCK2B: Low 55ns, high 610 (1.5MHz) Clock to latch S ROM address from P0~P15 (mapping) on rising edge.
/PORTADRS: $200000-$2FFFFF (P2+ ROM/Security chip) any access
/PORTOEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte read
/PORTOEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte read
/PORTWEL: $200000-$2FFFFF (P2+ ROM/Security chip) odd byte write
/PORTWEU: $200000-$2FFFFF (P2+ ROM/Security chip) even byte write
/PWAIT0, /PWAIT1: adds 0 to 3 cycle delay for P2 ROM reads, see wait cycles
R/W: 68k Read/Write
/ROMOE: $000000-$0FFFFF (P1 ROM) read
/ROMOEL: $000000-$0FFFFF (P1 ROM) odd byte read
/ROMOEU: $000000-$0FFFFF (P1 ROM) even byte read
/ROMWAIT: add 1-cycle delay for P1 ROM reads
/SROMOE: $C00000-$CFFFFF (System ROM) read
/SROMOEL: $C00000-$CFFFFF (System ROM) odd byte read
/SROMOEU: $C00000-$CFFFFF (System ROM) even byte read
SDA0~SDA15 : Z80 address bus
SDD0~SDD7: Z80 data bus
SDRAD0~SDRAD7: ADPCM-A ROM multiplexed bus (data/address)
SDRA8,SDRA9,SDRA20~SDRA23: ADPCM-A ROM address bus
SDPAD0~SDPAD7: ADPCM-B ROM multiplexed bus (data/address)
SDPA8,SDPA9,SDPA10,SDPA11: ADPCM-B ROM address bus
SYSTEM: low when onboard ROMs selected
SYSTEMB: inverted SYSTEM

@@ Line 124: / Line 124: @@
 |-
 |P0~P23
-|Multiplexed [[P BUS]]
+|Multiplexed [[P bus]]
 |Muxed
 |Multiple