68k/Z80 communication: Difference between revisions
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Inter-CPU communication is done through a byte-wide bi-directional register. | Inter-CPU communication is done through a byte-wide bi-directional register. | ||
There is no shared memory zone as in the Sega Megadrive. | |||
=68k to Z80 (request)= | =68k to Z80 (request)= | ||
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Any byte can be sent, the meaning of it is only determined by the way the Z80 code handles it (except for '''3 special cases''', as seen below). | Any byte can be sent, the meaning of it is only determined by the way the Z80 code handles it (except for '''3 special cases''', as seen below). | ||
When a byte is sent, the corresponding value is latched in {{Chipname|NEO-C1}} ({{Chipname|NEO-SUD}} in CD systems ?), and an NMI is triggered on the Z80 | When a byte is sent, the corresponding value is latched in {{Chipname|NEO-C1}} ({{Chipname|NEO-SUD}} in CD systems ?), and an NMI is triggered on the Z80. The value can then be read on the Z80's [[Z80 port map|port $00]]. | ||
(What chip is used on first gen chipset ?) | (What chip is used on first gen chipset ?) | ||
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==Command $01== | ==Command $01== | ||
It is sent by the system ROM just before the [[slot]] is switched. As the {{Chipname|M1 ROM}} has to be swapped, all sounds need to be stopped, | It is sent by the system ROM just before the [[slot]] is switched. As the {{Chipname|M1 ROM}} has to be swapped, all sounds need to be stopped, interrupts need to be enabled, $01 needs to be sent back to the 68k and the Z80 code has to wait in a loop '''in RAM'''. After receiving the reply, the system ROM can then switch slots without crashing the Z80. | ||
==Command $02== | ==Command $02== | ||
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;"MAKOTO V3" style handler | ;"MAKOTO V3" style handler | ||
Command01_Handler: | Command01_Handler: | ||
di ; Disable interrupts | |||
xor a | xor a | ||
out ($0C),a | out ($0C),a | ||
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ld (hl),#C3 ; (FFFD)=C3, opcode for JP | ld (hl),#C3 ; (FFFD)=C3, opcode for JP | ||
ld (#FFFE),hl ; (FFFE)=FFFD (JP FFFD) | ld (#FFFE),hl ; (FFFE)=FFFD (JP FFFD) | ||
ei | |||
ld a,#01 | ld a,#01 | ||
out (#0C),a ; Tell 68k that we're ready | out (#0C),a ; Tell 68k that we're ready | ||
Revision as of 15:28, 15 August 2016
Inter-CPU communication is done through a byte-wide bi-directional register.
There is no shared memory zone as in the Sega Megadrive.
68k to Z80 (request)
Writes to the Z80 are made through REG_SOUND. Any byte can be sent, the meaning of it is only determined by the way the Z80 code handles it (except for 3 special cases, as seen below).
When a byte is sent, the corresponding value is latched in NEO-C1 (NEO-SUD in CD systems ?), and an NMI is triggered on the Z80. The value can then be read on the Z80's port $00.
(What chip is used on first gen chipset ?)
Z80 to 68k (reply)
The Z80's port $0C is used to reply to the 68k. The value is also buffered in the same chips, but no interrupts are generated. The value can be read by using the same register, REG_SOUND.
Many sound drivers acknowledge sound commands by echoing them back with bit 7 set to 1 when they are processed.
Special commands
Commands $01 to $03 are always expected to be implemented in the Z80 code, as they are used by the system ROM for initialization purposes. During the MVS power up self-tests, if the Z80 doesn't reply to command $01 in time, the "Z80 ERROR" message is displayed and the system locks up.
Command $01
It is sent by the system ROM just before the slot is switched. As the M1 ROM has to be swapped, all sounds need to be stopped, interrupts need to be enabled, $01 needs to be sent back to the 68k and the Z80 code has to wait in a loop in RAM. After receiving the reply, the system ROM can then switch slots without crashing the Z80.
Command $02
It is used by cartridge systems to play the eyecatcher music. See boot music. No reply is expected.
Command $03
It is used to ask for a soft reset of the Z80, which needs to be done under 100ms. No reply is expected.
Minimal command handlers
These are sufficient handlers for both init commands:
;"MAKOTO V3" style handler
Command01_Handler:
di ; Disable interrupts
xor a
out ($0C),a
out ($00),a
; Init banks and stuff here...
ld sp,#FFFC
ld hl,stayinram
push hl
retn ; RETN to stayinram
stayinram:
ld hl,#FFFD
ld (hl),#C3 ; (FFFD)=C3, opcode for JP
ld (#FFFE),hl ; (FFFE)=FFFD (JP FFFD)
ei
ld a,#01
out (#0C),a ; Tell 68k that we're ready
jp #FFFD ; Quickly jump to RAM loop
Command03_Handler: di ; Disable interrupts ld sp, $FFFF ; Clear call stack ld hl,0 push hl retn ; RETN to 0