68k/Z80 communication

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Communication between the 68k CPU and the Z80 CPU is done through 2 byte-wide registers.

There is no shared memory zone like in the Sega Genesis/Megadrive.

68k to Z80 (request)

Writes to the Z80 are done through REG_SOUND. Any byte can be sent, the meaning of it is only determined by the way the Z80 code handles it (except for 3 special cases, as seen below).

When a byte is sent, the corresponding value is latched in NEO-C1 (NEO-SUD in CD systems ?), and an NMI is triggered in the Z80 if enabled. The value can then be read on the Z80's side with port $00.

(What chip is used on first gen chipset ?)

Z80 to 68k (reply)

The Z80's port $0C is used to reply to the 68k. The value is also buffered in the same chip, but no interrupt is generated. The value can be read on the 68k's side by using the same register, REG_SOUND.

Many sound drivers acknowledge sound commands by echoing them back with bit 7 set to 1 when they are processed.

Special commands

Commands $01, $02 and $03 are always expected to be implemented in the Z80 code, as they are used by the system ROM for initialization purposes. During the MVS power up self-tests, if the Z80 doesn't reply to command $01 in time, the "Z80 ERROR" message is displayed and the system locks up.

Command $01: Prepare switch

It is sent by the system ROM just before the slot is switched. As the M1 ROM has to be swapped, all sounds need to be stopped, interrupts need to be enabled, $01 needs to be sent back to the 68k and the Z80 has to wait in a loop in RAM. After receiving the reply, the system ROM can then switch slots without crashing the Z80.

Command $02: Play eyecatcher music

It is used in cartridge systems to play the eyecatcher music. See boot music. No reply is expected.

Command $03: Reset

It is used to ask for a soft reset of the Z80, which needs to be done under 100ms as per SNK's recommendation. No reply is expected.

Minimal command handlers

These are sufficient handlers for both init commands:

        di			; Disable interrupts
        xor  a
        out  ($0C),a            ; Clear both buffers
        out  ($00),a
        ; Silence YM2610 here
        ld   sp,$FFFC           ; Reset SP
        ld   hl,stayinram
        push hl
        retn                    ; RETN to stayinram

        ld   hl,$FFFD
        ld   (hl),$C3	        ; (FFFD)=$C3, opcode for JP
        ld   ($FFFE),hl	        ; (FFFE)=$FFFD (makes "JP FFFD")
        ld   a,$01
        out  ($0C),a            ; Tell 68k that we're ready
        jp   $FFFD              ; Quickly jump to RAM loop
	di			; Disable interrupts
	ld   sp,$FFFF		; Clear call stack
	ld   hl,0
	push hl
	retn			; RETN to 0