P bus: Difference between revisions

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The P bus is a 24-bit internal graphics data bus, connecting the video-related chips, and the C and S ROM address latches in cartridges.
The P bus is a 24-bit internal graphics data bus, connecting the video-related chips and the C and S ROM address latches in cartridges.


C and S ROM adresses are extracted by [[NEO-273]] or regular 273's thanks to the PCK1B and PCK2B [[signal names|signals]].
It carries multiplexed data, which is sequenced by [[LSPC]] in a precise and repetitive manner.


== Contents ==
C and S ROM adresses are extracted in cartridges by {{Chipname|NEO-273}} or regular 273's thanks to the {{Sig|PCK1B|PCK1B}} and {{Sig|PCK2B|PCK2B}} signals.
 
=Values=


{|class="wikitable"
{|class="wikitable"
!P BUS||P23||P22||P21||P20||P19||P18||P17||P16||P15||P14||P13||P12||P11||P10||P9||P8||P7||P6||P5||P4||P3||P2||P1||P0
!P BUS||P23||P22||P21||P20||P19||P18||P17||P16||P15||P14||P13||P12||P11||P10||P9||P8||P7||P6||P5||P4||P3||P2||P1||P0
|-
|-
|B1 pin||TDI11||TDI10||TDI9||TDI8||TDI7||TDI6||TDI5||TDI4||P15||P14||P13||P12||P11||P10||P9||P8||TA7||TA6||TA5||TA4||TA3||TA2||TA1||TA0
|{{Chipname|NEO-B1 }}pin||TDI11||TDI10||TDI9||TDI8||TDI7||TDI6||TDI5||TDI4||P15||P14||P13||P12||P11||P10||P9||P8||TA7||TA6||TA5||TA4||TA3||TA2||TA1||TA0
|-
|-
|style="background-color: black;" colspan=25|
|style="background-color: grey;" colspan=25|
|-
|-
|[[LO]] address|| || || || || || || || ||A15||A14||A13||A12||A11||A10||A9||A8||A7||A6||A5||A4||A3||A2||A1||A0
|rowspan=2|'''[[LO]] address'''||rowspan=2 colspan=8| ||A15||A14||A13||A12||A11||A10||A9||A8||A7||A6||A5||A4||A3||A2||A1||A0
|-
|-
| ||colspan=8| ||colspan=8|Table # (shrink value)||colspan=8|Index in table (line)
|colspan=8|Table # (shrink value)||colspan=8|Index in table (line)
|-
|-
|style="background-color: black;" colspan=25|
|style="background-color: grey;" colspan=25|
|-
|-
|FIX palette||0||0||0||0||D3||D2||D1||D0|| || || || || || || || || || || || || || || ||
|'''LO data'''||D7||D6||D5||D4||D3||D2||D1||D0||colspan=16|  
|-
|-
|SPR palette||D7||D6||D5||D4||D3||D2||D1||D0|| || || || || || || || || || || || || || || ||
| ||colspan=4|Tilemap index||colspan=4|Tile line||colspan=16|
|-
|-
|style="background-color: black;" colspan=25|
|style="background-color: grey;" colspan=25|
|-
|-
|X position|| || || || || || || || ||D7||D6||D5||D4||D3||D2||D1||D0||?||?||?||?||?||?||?||?||
|'''FIX palette'''||colspan=4| ||D3||D2||D1||D0||colspan=16|  
|-
|-
|style="background-color: black;" colspan=25|
|'''SPR palette'''||D7||D6||D5||D4||D3||D2||D1||D0||colspan=16|  
|-
|-
|LO data||D7||D6||D5||D4||D3||D2||D1||D0|| || || || || || || || || || || || || || || ||
|style="background-color: grey;" colspan=25|
|-
|-
| ||colspan=4|Tilemap index||colspan=4|Tile line||colspan=16|
|'''X position'''||colspan=8| ||D7||D6||D5||D4||D3||D2||D1||D0||colspan=8|?
|-
|-
|style="background-color: black;" colspan=25|
|style="background-color: grey;" colspan=25|
|-
|-
|C address||A24||A23||A22||A21||A3||A2||A1||A0||A20||A19||A18||A17||A16||A15||A14||A13||A12||A11||A10||A9||A8||A7||A6||A5
|rowspan=2|'''C address'''||A24||A23||A22||A21||A3||A2||A1||A0||A20||A19||A18||A17||A16||A15||A14||A13||A12||A11||A10||A9||A8||A7||A6||A5
|-
|-
| ||colspan=4|Tile number||colspan=4|8-Pixel line #||colspan=16|Tile number
|colspan=4|Tile number||colspan=4|8-Pixel line #||colspan=16|Tile number
|-
|-
|style="background-color: black;" colspan=25|
|style="background-color: grey;" colspan=25|
|-
|-
|S address|| || || || || || || || ||A4||A2||A1||A0||A16||A15||A14||A13||A12||A11||A10||A9||A8||A7||A6||A5
|rowspan=2|'''S address'''||rowspan=2 colspan=8| ||A4||A2||A1||A0||A16||A15||A14||A13||A12||A11||A10||A9||A8||A7||A6||A5
|-
|-
| ||colspan=8| ||Half||colspan=3|8-Pixel line #||colspan=12|Tile number
|Half||colspan=3|8-Pixel line #||colspan=12|Tile number
|}
|}
Note that C A4 ({{Sig|CA4|CA4}}) and S A3 ({{Sig|S1H|2H1}}) are separate signals.


[[Category:Video system]]
[[Category:Video system]]

Revision as of 10:13, 16 October 2016

The P bus is a 24-bit internal graphics data bus, connecting the video-related chips and the C and S ROM address latches in cartridges.

It carries multiplexed data, which is sequenced by LSPC in a precise and repetitive manner.

C and S ROM adresses are extracted in cartridges by NEO-273 or regular 273's thanks to the PCK1B and PCK2B signals.

Values

P BUS P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
NEO-B1 pin TDI11 TDI10 TDI9 TDI8 TDI7 TDI6 TDI5 TDI4 P15 P14 P13 P12 P11 P10 P9 P8 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0
LO address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Table # (shrink value) Index in table (line)
LO data D7 D6 D5 D4 D3 D2 D1 D0
Tilemap index Tile line
FIX palette D3 D2 D1 D0
SPR palette D7 D6 D5 D4 D3 D2 D1 D0
X position D7 D6 D5 D4 D3 D2 D1 D0 ?
C address A24 A23 A22 A21 A3 A2 A1 A0 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5
Tile number 8-Pixel line # Tile number
S address A4 A2 A1 A0 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5
Half 8-Pixel line # Tile number

Note that C A4 (CA4) and S A3 (S1H) are separate signals.

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