NEO-G0: Difference between revisions
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[[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]] | [[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]] | ||
Only found in AES systems ? | Gates the [[68k]] data bus to the memory card slot and palette RAM. Only found in AES systems ? | ||
PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in [[NEO-E0]] ? | |||
PALWE = PAL OR R/W. | |||
=Pinout= | |||
[[File:Neo-g0_pinout.png]] | |||
*D0~D15: 68k data bus | |||
*PALD0~PALD7: lower byte of palette data | |||
*PAUD0~PAUD7: upper byte of palette data | |||
*MCD0~MCD15: memory card data (and address ?) bus | |||
[[Category:Chips]] | [[Category:Chips]] | ||
Revision as of 18:05, 25 March 2011
Gates the 68k data bus to the memory card slot and palette RAM. Only found in AES systems ?
PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in NEO-E0 ?
PALWE = PAL OR R/W.
Pinout
- D0~D15: 68k data bus
- PALD0~PALD7: lower byte of palette data
- PAUD0~PAUD7: upper byte of palette data
- MCD0~MCD15: memory card data (and address ?) bus