NEO-G0

Package	QFP64R
Manufacturer
First use	1992 ?
Used on	MV2B ...

Quadruple 245 with additional OR and AND gates. Predecessor of NEO-BUF.

Internal logic

Schematic is wrong: A and B sides are flipped !

Pin 51 is enable for MCD0~MCD15 Pin 39 is enable for PALD0~PALD15 Pin 40 is direction select for D0~D7 Pin 52 is direction select for D8~D15

Pinouts

AES

Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.

Edit this pinout

D0~D15: 68k data bus PALD0~PALD7: Lower palette RAM data bus PAUD0~PAUD7: Upper palette RAM data bus MCD0~MCD15: Memory card data bus PAL: Palette RAM address decode from NEO-C1 R/W: R/W from 68k PALWE: Palette RAM /WE, output made from PAL OR R/W ROMOEL, ROMOEU: from PRO-C0 ROMOE: Cartridge P ROM /OE, output made from ROMOEU AND ROMOEL

MV2B

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  J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from NEO-I0. OpenOffice Draw file: File:Neo-g0 mv2b J4.odg

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  J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from NEO-F0. OpenOffice Draw file: File:Neo-g0 mv2b J12.odg

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  B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from PRO-C0. OpenOffice Draw file: File:Neo-g0 mv2b C7.odg