Wait cycle

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The 68k is able to wait for data by making it insert wait cycles during bus access. This allows the use of slow, cheaper memories.

The NeoGeo provides wait state generation for 3 memory zones:

  • 000000~0FFFFF: ROM zone (P ROM) - Configurable, 0 or 1 cycle
  • 200000~2FFFFF: PORT zone (P ROM or special chips) - Configurable, 0, 1, 2 or more cycles
  • 800000~BFFFFF: Memory card - Fixed, 2 cycles


Configuration is done by setting the levels of the following cartridge pins. '1' means pulled to 5V, '0' means pulled to ground. All signals are active low.

ROMWAIT ROM zone wait
1 Full speed
0 1 cycle
PWAIT1 PWAIT0 PORT zone wait
1 1 Full speed
1 0 1 cycle
0 1 2 cycles
0 0 As long as PDTACK is high

Use cases

Some games rely on wait cycles to perform sufficiently spaced VRAM accesses. Disabling the wait on those cartridges causes the accesses to become too close to each other and results in graphics corruption.

No originally released cartridges are known to use PDTACK.