YM2610 registers

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Revision as of 02:35, 17 November 2016 by Furrtek (talk | contribs) (Layout, timer and individual bit details)
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Timers

To do: Page.

Address (Z80 port 4) Data (Z80 port 5)
$24
Bit 7 6 5 4 3 2 1 0
Def TA counter load bits 9-2
$25
Bit 7 6 5 4 3 2 1 0
Def - TA counter load bits 1-0
$26
Bit 7 6 5 4 3 2 1 0
Def TB counter load bits 0-7
$27
Bit 7 6 5 4 3 2 1 0
Def CSM mode 3-slot modeReset TBReset TAEnable TB IRQEnable TA IRQLoad TBLoad TA
  • TA = Timer A (10bit), TB = Timer B (8bit)
  • Timers will tick until they have reached zero, at which point an IRQ will be generated if enabled. Reading port $04 will show which timer caused it (see below).
  • The actual timer counter registers are not directly accessible. They can be reset to zero or initialised from load registers $24~$26
    • Writing 0 to the load bits in register $27 will reset the timer counter registers to zero
    • Writing 1 to the load bits will copy the respective timer load register to the timer counter. This only works when the timer is at zero.
  • When a timer expires, it is automatically reloaded from the load registers and continues.
  • Timer flag reset refers to the same flags that are read from port $04
  • CSM mode is for automatic key on for operators on the second FM channel when timer A expires ?
  • Timer A IRQ frequency: 8M / 2 / 12 (prescaler) / 12 / TA load = 27.1Hz ~ 27.8kHz ?
  • Timer A IRQ frequency: 8M / 16 / 12 (prescaler) / 12 / TB load = 13.6Hz ~ 3.47kHz ?

SSG part

See SSG for details on this part's operation.

Address (Z80 port 4) Data (Z80 port 5)
$00
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Channel A
$01
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
$02
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Channel B
$03
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
$04
Bit 7 6 5 4 3 2 1 0
Def Fine tune
Channel C
$05
Bit 7 6 5 4 3 2 1 0
Def - Coarse tune
$06
Bit 7 6 5 4 3 2 1 0
Def - Noise tune
Noise channel
$07
Bit 7 6 5 4 3 2 1 0
Def - /EN noise C/EN noise B/EN noise A/EN C/EN B/EN A
/Enable for Noise and Tone
$08
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Channel A
$09
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Channel B
$0A
Bit 7 6 5 4 3 2 1 0
Def - ModeVolume
Channel C
$0B
Bit 7 6 5 4 3 2 1 0
Def Volume envelope period fine tune
$0C
Bit 7 6 5 4 3 2 1 0
Def Volume envelope period coarse tune
$0D
Bit 7 6 5 4 3 2 1 0
Def - Volume envelop shape
See diagram.

FM part

See FM for details on this part's operation.

Common FM registers

Address (Z80 port 4) Data (Z80 port 5)
$22
Bit 7 6 5 4 3 2 1 0
Def - OnControl
LFO Frequency
$28
Bit 7 6 5 4 3 2 1 0
Def Slot -Channel
Key On/Off

LFO frequency values are as follows:

  • 0 – 3.98Hz
  • 1 – 5.56Hz
  • 2 – 6.02Hz
  • 3 – 6.37Hz
  • 4 – 6.88Hz
  • 5 – 9.63Hz
  • 6 – 48.1Hz
  • 7 – 72.2Hz

Overall channel registers

The first value listed in the Address column is for channels 1/3; the second is for channels 2/4.

Address (Z80 port 4 or 6) Data (Z80 port 5 or 7)
$A1,$A2
Bit 7 6 5 4 3 2 1 0
Def F-Num 1
F-Numbers and Block (1/2)
$A5,$A6
Bit 7 6 5 4 3 2 1 0
Def - BlockF-Num 2
F-Numbers and Block (2/2)
(must set this first)
$A9,$AA
Bit 7 6 5 4 3 2 1 0
Def 2CH * F-Num 1
2CH - 2 Slot F-Numbers/Block (1/2)
$AD,$AE
Bit 7 6 5 4 3 2 1 0
Def - 2CH * Block2CH * F-Num 2
2CH - 2 Slot F-Numbers/Block (1/2)
(must set this first)
$B1,$B2
Bit 7 6 5 4 3 2 1 0
Def - FBALGO
Feedback (FB) and Algorithm (ALGO)
$B5,B6
Bit 7 6 5 4 3 2 1 0
Def L RAMS-PMS
Left (L)/Right (R) output, AM Sense (AMS), and PM Sense (PMS)

Channel registers

Depending on which channel you want to write to, the ports used are different:

  • Channels 1 & 2: Ports 4/5
  • Channels 3 & 4: Ports 6/7

Per-operator registers

The ranges given for the address represent all of the parameter values. Each channel's operators are laid out as follows:

Operator 1 2 3 4
Channels 1, 3 $x1 $x5 $x9 $xD
Channels 2, 4 $x2 $x6 $xA $xE
Address (Z80 port 4 or 6) Data (Z80 port 5 or 7)  
$31-$3E
Bit 7 6 5 4 3 2 1 0
Def - DTMUL
Detune (DT) and Multiple (MUL)
$41-$4E
Bit 7 6 5 4 3 2 1 0
Def - Total Level
Total Level (Volume)
$51-$5E
Bit 7 6 5 4 3 2 1 0
Def KS -AR
Key Scale (KS) and Attack Rate (AR)
$61-$6E
Bit 7 6 5 4 3 2 1 0
Def AM -DR
AM On (AM) and Decay Rate (DR)
$71-$7E
Bit 7 6 5 4 3 2 1 0
Def - SR
Sustain Rate (SR)
$81-$8E
Bit 7 6 5 4 3 2 1 0
Def SL RR
Sustain Level (SL) and Release Rate (RR)
$91-$9E
Bit 7 6 5 4 3 2 1 0
Def - SSG-EG
SSG-EG

ADPCM part

See ADPCM for details on this part's operation.

Address (Z80 port 4) Data (Z80 port 5) Value on reset
$1C
Bit 7 6 5 4 3 2 1 0
Def B -A6A5A4A3A2A1
$00
  • Write to flag control to reset/mask channel end flags
    • Write 1 to reset and/or mask selected flag
    • Write 0 to unmask selected flag
    • Masking a flag will prevent it from being raised when a channel reaches its end address. This means you have to write 1 to clear the flag, then 0 to keep it active.
    • Flags must be manually cleared, playing a new sample on the channel won't clear it.

ADPCM-A part

See ADPCM for details on this part's operation.

Address (Z80 port 6) Data (Z80 port 7) Value on reset
$00
Bit 7 6 5 4 3 2 1 0
Def Dump -CH6 ONCH5 ONCH4 ONCH3 ONCH2 ON CH1 ON
$00 'Dump' is the key on/off bit. Write 0 to start playing specified channels and write 1 to stop playing.
$01
Bit 7 6 5 4 3 2 1 0
Def - Master volume
$00 Actually an attenuator, 0 is the loudest.
$08~$0D (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def L R-Channel volume
$00 Actually an attenuator, 0 is the loudest. L/R routes the output to the left and/or right channels.
$10~$15 (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 LSB
$00 All ADPCM addresses must match a 256-byte boundary (bits 0~7 = 0)
$18~$1D (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 MSB
$00
$20~$25 (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 LSB
$00
$28~$2D (one for each channel)
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 MSB
$00

ADPCM-B part

See ADPCM for details on this part's operation.

Address (Z80 port 4) Data (Z80 port 5) Value on reset
$10
Bit 7 6 5 4 3 2 1 0
Def Start -Repeat-Reset
$00 Repeat: loop when end address is reached. Reset: clears Start and Repeat.
$11
Bit 7 6 5 4 3 2 1 0
Def L R-
$00 Left/Right channel output
$12
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 LSB
? All ADPCM addresses must match a 256-byte boundary (bits 0~7 = 0)
$13
Bit 7 6 5 4 3 2 1 0
Def Sample's start address/256 MSB
?
$14
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 LSB
?
$15
Bit 7 6 5 4 3 2 1 0
Def Sample's stop address/256 MSB
?
$19
Bit 7 6 5 4 3 2 1 0
Def Delta-N (L)
? Playback rate is f = 8M / 12 / 12 / (65535 / Delta-N) = 55555 * (Delta-N / 65535) Hz
$1A
Bit 7 6 5 4 3 2 1 0
Def Delta-N (H)
?
$1B
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B channel volume
? Loudest is $FF

Reading

The only writable registers that can also be read are from the SSG. All other ports and addresses return different data.

Z80 port # Data Notes
$04
Bit 7 6 5 4 3 2 1 0
Def Busy -Timer B flagTimer A flag
When a timer expires and IRQ is enabled for the timer, the respective bit is set
$05
Bit 7 6 5 4 3 2 1 0
Def SSG register data
Attempting to read non-SSG registers will fail
$06
Bit 7 6 5 4 3 2 1 0
Def ADPCM-B end -CH6 endCH5 endCH4 endCH3 endCH2 endCH1 end
When a channel has reached the end address and stops, the respective bit is set, unless masked
$07 not implemented Always returns $00