Z80/YM2610 interface: Difference between revisions
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The | The {{Chipname|Z80}} can access the {{Chipname|YM2610}} through two pair of [[Z80 port map|ports]]. They're usually called Address A, Data A, and Address B, Data B. They're respectively Z80 ports 4, 5, 6 and 7. | ||
They're respectively | |||
* | * Pair A (Z80 ports 4 and 5) concerns the [[SSG]], [[ADPCM codecs|ADPCM]]-B, and [[FM audio|FM]] channels 1 and 2. | ||
* | * Pair B (Z80 ports 6 and 7) concerns the ADPCM-A, and FM channels 3 and 4. | ||
See [[YM2610 registers]] for a complete definition of the registers. | |||
The Z80's {{Sig|SDA0|SDA0}} and SDA1 lines are directly connected to the YM2610's A0 and A1 inputs. {{Chipname|NEO-D0}} uses SDA2 to decode the access to the YM2610. | |||
The | =Timing requirements= | ||
The YM2610 needs a delay between writes, or else they will be skipped. Some [[homebrew software]] produce sound in [[emulators]] but not on the real hardware because of this. | |||
From Japanese datasheet: | |||
* Address write: 17 cycles (8MHz: 2.125us) | |||
* Data write: 83 cycles (8MHz: 10.375us) | |||
Many original [[sound driver]]s use small routines with fixed delays to write to the YM2610: | |||
<pre> | |||
; DE -> YM2610 pair A | |||
; This also works with pair B (ports 6 & 7) | |||
di | |||
ld a,d | |||
out ($04),a | |||
; At least 21 T-states here ! (6 NOPs, 5.25us) | |||
ld a,e | |||
out ($05),a | |||
; At least 73 T-states here ! (19 NOPs, 18.25us) | |||
ei | |||
</pre> | |||
Polling the YM2610's busy flag is also a solution. | |||
[[Category:Audio system]] | [[Category:Audio system]] | ||
[[Category:Code]] | |||
Latest revision as of 09:34, 8 November 2016
The Z80 can access the YM2610 through two pair of ports. They're usually called Address A, Data A, and Address B, Data B. They're respectively Z80 ports 4, 5, 6 and 7.
- Pair A (Z80 ports 4 and 5) concerns the SSG, ADPCM-B, and FM channels 1 and 2.
- Pair B (Z80 ports 6 and 7) concerns the ADPCM-A, and FM channels 3 and 4.
See YM2610 registers for a complete definition of the registers.
The Z80's SDA0 and SDA1 lines are directly connected to the YM2610's A0 and A1 inputs. NEO-D0 uses SDA2 to decode the access to the YM2610.
Timing requirements
The YM2610 needs a delay between writes, or else they will be skipped. Some homebrew software produce sound in emulators but not on the real hardware because of this.
From Japanese datasheet:
- Address write: 17 cycles (8MHz: 2.125us)
- Data write: 83 cycles (8MHz: 10.375us)
Many original sound drivers use small routines with fixed delays to write to the YM2610:
; DE -> YM2610 pair A ; This also works with pair B (ports 6 & 7) di ld a,d out ($04),a ; At least 21 T-states here ! (6 NOPs, 5.25us) ld a,e out ($05),a ; At least 73 T-states here ! (19 NOPs, 18.25us) ei
Polling the YM2610's busy flag is also a solution.