Latest revision as of 02:07, 8 July 2018

Chip found on late MVS boards.

Pinout

@@ Line 1: / Line 1: @@
-[[File:neo-sdr-t.jpg|thumb]]
+{{ChipInfo
+|picture=neo-sdr-t.jpg
+|pkg=QFP100R
+|manu=toshiba
+|date=1994 ?
+|gates=
+|used_on={{PCB|MV1B}} {{PCB|MV1C}} {{PCB|Neo Print}}...
+}}
-Chip found on MV1B and MV1C [[MVS hardware|slots]]. Handles [[Z80]] subsystem address and port decoding, Z80/68K communication latches and interrupt generation, similarly to [[NEO-D0]]. Handles 2 player I/O as well.
+Chip found on late [[MVS hardware|MVS]] boards.
-Draft pinout: [[File:neo-sdr.odg]]
+* [[Joypad]] I/O
+* {{Chipname|Z80}} address and port decoding
+* [[68k/Z80 communication]] latches and interrupt generation, similarly to {{Chipname|NEO-D0}}
+* [[68k]] interrupts latch ?
-== Pinout ==
+=Pinout=
-NEO-SDR
+{{Pinout|NEO-SDR|900px}}
-* 1 VCC
-* 2 VCC
-* 3 GND ?
-* 4 VCC
-* 5 VCC
-* 6 VCC
-k:
-* 65 D0
-* 64 D1
-* 63 D2
-* 62 D3
-* 61 D4
-* 60 D5
-* 59 D8
-* 58 D9
-* 57 D10
-* 56 D11
-* 55 D12
-* 54 D13
-* 53 D14
-* 52 D15
-* 51 GND
-* 50 GND
-Z80:
-* 49 SDD7
-* 48 SDD6
-* 47 SDD5
-* 46 SDD4
-* 45 SDD3
-* 44 SDD2
-* 43 SDD1
-* 42 SDD0
-* 40 NMI
-* 29 MREQ
-* 28 IORQ
-* 27 Z80RD
-* 26 Z80WR
 [[Category:Chips]]