CHA board: Difference between revisions

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From [[Link|MAME's source]]:
__NOTOC__


=MVS=
Cartridge PCB which holds the [[C ROM|C]] (sprite graphics), [[M1 ROM|M]] (Z80 code) and [[S ROM|S]] (fix graphics) ROMs.


==CHA boards==
List from [[https://github.com/mamedev/mame/blob/master/src/mame/drivers/neodriv.hxx MAME's source]].
===CHA-32===
===CHA-8M===
===CHA42G===
===CHA42G-1===
===CHA 42G-2===
===CHA 42G-3===
===CHA 42G-3B===
===CHA256===
===CHA256B===
===CHA512Y===
*Max 8 8MiB C ROMs
*Max 128KiB M1 ROM
*Max 128KiB S1 ROM
*NEO-273
*NEO-ZMC
*LS139,LS174
===CHAFIO===
*used with NEO-CMC 90G06C7042 or NEO-CMC 90G06C7050
===MVS CHAFIO REV1.0 (KOF-2001)===
===CHAFIO (SNK 2002)===
===CHAFIO===
*Max 8 8MiB C ROMs
*Max 256KiB (?) M1 ROM
*used only with NEO-CMC 90G06C7050


==PROG boards==
=MVS=
===PROG-NAM===
===PROG-HERO===
===PROG-EP===
===PROG-8MB===
===PROG8M42===
===PROG16===
===PROG 42G===
===PROG 42G-COM===
===PROG 42G-1===
===PROG-G2===
===PROG 4096===
===PROG 4096 B===
===PROGGSC===
===PROGSM===
===PROGSS3===
===PROGTOP===
===PROGSF1===
===PROGEOP===
===PROGLBA===
===PROGBK1===
 
The only non-protected board that can bankswitch and use all V ROM space.  Really common and very useful for homebrew stuff or converts.
 
====P ROM====
 
P1 can be 512K, 1M or 2M (27C400/27C800/27C160).
*If P1 is 2M then some jumper must be set (JB3? didn't look into it. see kof95) and P2 should be empty.  First half of P1 is mapped to 0x200000-0x2FFFFF and second half is mapped to 0x000000-0x0FFFFFF.
*If P1 is 512K or 1M, then P2 can contain a bankswitched ROM (same type as P1 plus 27C322).  P1 appears at 0x000000-0x0FFFFF.  P2 banked rom appears in 0x200000-0x2FFFFF.
 
====V ROM====
 
V ROMs can be 1M, 2M or 4M (27C800/27C160/27C322).  Size of largest ROM is selected with a pair of jumpers and the other 4 should be left unconnected.  512K can also be used but only if there is one ROM and only in the last used slot.


{| class="wikitable"
{| class="wikitable"
!Name
!Chips
!Max C ROM
!Max S ROM
!Max M ROM
|-
|[[CM2]] (Prototype)
|-
|[[CHA-EP]] (Prototype)
|-
|[[CHA-32]]
|-
|-
!ROM size
|[[CHA-8M]]
!Jumper A
!Jumper B
|-
|-
|8M
|CHAEP8M (Prototype)||[[NEO-ZMC]],[[NEO-273]]||8*1024||128||128
|JV1
|JV2
|-
|-
|16M
|[[CHA256]]||[[NEO-ZMC]],[[NEO-273]]||8*4096||?||?
|JV3
|JV4
|-
|-
|32M
|[[CHA256B]]||[[NEO-ZMC]],[[NEO-273]]||8*4096||?||?
|JV5
|-
|JV6
|[[CHA42G-1]]||[[NEO-ZMC]],[[NEO-273]]||4*1024||128||128
|-
|CHA42G-2
|-
|CHA42G-3?
|-
|CHA42G-3B
|-
|[[CHA512Y]]||[[NEO-ZMC]],[[NEO-273]]||8*8192||128||128
|-
|CHA64-C
|[[NEO-ZMC]]
|-
|[[CHAFIO]]||[[NEO-CMC]]42, [[NEO-CMC]]50
|-
|CHAMC2||[[NEO-ZMC]],[[NEO-273]]||2*16384||512||512
|-
|PSTM-ROMC||-||-||-||-
|}
|}


====Pinouts====
=Home Console=


Bankswitching is done with the LS74.  It's not needed if the game isn't banked.  Any write to an odd 0x200000-0x2FFFFF address will set the bank.
{| class="wikitable"
{| class="wikitable"
!Name
!Chips
!Max C ROM
!Max S ROM
!Max M ROM
|-
|-
!Cart edge
|[[CHA-EP]] (Prototype)||-||-||-||-
!LS74
!P2
|-
|-
|A5
|[[CHA-32]]||-||-||-||-
|pin 2
|N/A
|-
|-
|A6
|[[CHA-8M]]||-||-||-||-
|pin 12
|N/A
|-
|-
|N/A
|[[CHA42G]]||-||-||-||-
|pin 5
|pin 42
|-
|-
|N/A
|[[CHA42G-1]]||-||-||-||-
|pin 9
|-
|pin 32
|[[CHA42G-2]]||-||-||-||-
|}
|-
 
|[[CHA42G-2C]]||-||-||-||-
One of 4 V ROMs is enabled with a set of LS139 outputs.  The pair of V ROM jumpers effectively choose a set of 2 NEO-PCM address outputs to input to the LS139.
 
{| class="wikitable"
|-
|-
!Jumper
|[[CHA-EPG]] (Prototype)||-||-||-||-
!LS139
!V ROM
|-
|-
|JV1
|[[CHA42G-3]]||-||-||-||-
|pin 2
|N/A
|-
|-
|JV2
|[[CHA42G-4]]||-||-||-||-
|pin 3
|N/A
|-
|-
|JV3
|[[CHA256]]||-||-||-||-
|pin 2
|N/A
|-
|-
|JV4
|[[CHA256 B]]||-||-||-||-
|pin 3
|N/A
|-
|-
|JV5
|[[CHA256🄱]]||-||-||-||-
|pin 2
|N/A
|-
|-
|JV6
|[[CHA256BY]]||-||-||-||-
|pin 3
|N/A
|-
|-
|N/A
|[[CHA256RY]]||-||-||-||-
|pin 4
|V1 pin 14
|-
|-
|N/A
|[[CHA512Y]]||-||-||-||-
|pin 5
|V2 pin 14
|-
|-
|N/A
|[[CHAFIO]]||-||-||-||-
|pin 6
|V3 pin 14
|-
|-
|N/A
|pin 7
|V4 pin 14
|}
|}


The LS08 is used to AND the two PORT /OE signals.
==CHA-32==
[[File:neo-mvs-cha32.png|400px]]
 
==CHAFIO REV1.0 (KOF-2001)==
 
==CHAMC2(Prototype Board)==
[[http://www.neogeoprotos.com/games/topsecret2.htm Billy Pit's Neo-Geo Proto Page]] or [[http://www.assemblergames.com/forums/showthread.php?t=23106&page=11]]


*4x 1/2/4MiB V ROMs
==PSTM-ROMC==
*1/2MiB P1 ROM
*1/2/4MiB P2 ROM
*2x 512KiB EP1/EP2 ROM
*NEO-PCM
*LS139,LS08,LS74


===PROGBK2===
The only cart board which hasn't a [[S ROM]].
===PROGBK2 REV1.0 (KOF-2001)===
===PROGBK2===
===PROGBK2R===
===PROGBK3R===
===PROGBK3S===
===PROGBK2S===
===PROGV (Brezzasoft)===
Same board manufacturer as SNK ?
*42pin V1 and P1 ROMs (DIP or TSOP)
*64KiB Battery-backed RAM (Mapped to $200000~?)
*External I/O port (8 ?)
*Room for 2x8DIP switchs


[[Category:Chips]]
[[Category:Chips]]
[[Category:Cartridge systems]]
[[Category:Cartridge systems]]
[[Category:Cartridge boards]]

Latest revision as of 19:25, 6 September 2025


Cartridge PCB which holds the C (sprite graphics), M (Z80 code) and S (fix graphics) ROMs.

List from [MAME's source].

MVS

Name Chips Max C ROM Max S ROM Max M ROM
CM2 (Prototype)
CHA-EP (Prototype)
CHA-32
CHA-8M
CHAEP8M (Prototype) NEO-ZMC,NEO-273 8*1024 128 128
CHA256 NEO-ZMC,NEO-273 8*4096 ? ?
CHA256B NEO-ZMC,NEO-273 8*4096 ? ?
CHA42G-1 NEO-ZMC,NEO-273 4*1024 128 128
CHA42G-2
CHA42G-3?
CHA42G-3B
CHA512Y NEO-ZMC,NEO-273 8*8192 128 128
CHA64-C NEO-ZMC
CHAFIO NEO-CMC42, NEO-CMC50
CHAMC2 NEO-ZMC,NEO-273 2*16384 512 512
PSTM-ROMC - - - -

Home Console

Name Chips Max C ROM Max S ROM Max M ROM
CHA-EP (Prototype) - - - -
CHA-32 - - - -
CHA-8M - - - -
CHA42G - - - -
CHA42G-1 - - - -
CHA42G-2 - - - -
CHA42G-2C - - - -
CHA-EPG (Prototype) - - - -
CHA42G-3 - - - -
CHA42G-4 - - - -
CHA256 - - - -
CHA256 B - - - -
CHA256🄱 - - - -
CHA256BY - - - -
CHA256RY - - - -
CHA512Y - - - -
CHAFIO - - - -

CHA-32

CHAFIO REV1.0 (KOF-2001)

CHAMC2(Prototype Board)

[Billy Pit's Neo-Geo Proto Page] or [[1]]

PSTM-ROMC

The only cart board which hasn't a S ROM.

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