Video DAC: Difference between revisions
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[[File:mvs_viddac.jpg|right|thumb|Resistor array forming the video DAC on a [[MV1FZS]].]] | [[File:mvs_viddac.jpg|right|thumb|Resistor array forming the video DAC on a [[MV1FZS]].]] | ||
The NeoGeo uses a discrete video '''D'''igital-to-'''A'''nalog '''C'''onverter made of resistors fed by two 74LS273 latches which store the color value from the [[palette RAM]] and | The NeoGeo uses a discrete video '''D'''igital-to-'''A'''nalog '''C'''onverter made of resistors fed by two [[74LS273|74LS273]] latches which store the color value from the [[palette RAM]] and [[74LS05|74LS05]] inverters. This is controlled by either {{Chipname|NEO-B1}}, {{Chipname|NEO-GRC}} or {{Chipname|NEO-GRZ}}. | ||
[[File:aes_viddac.png|right|thumb|Video DAC on a AES board.]] | [[File:aes_viddac.png|right|thumb|Video DAC on a AES board.]] | ||
[[File:aes_viddac_schematic.png]] | [[File:aes_viddac_schematic.png]] | ||
Note: The schematic has a typo and shows a 74LS06 instead of [[74LS05|74LS05]] but both can be used. | |||
Each color component has its own set of 7 resistors. 6 of them are used for the actual color value (5 + 1 [[Colors|common bit]]). The last (SHADOW signal) is related to the {{Reg|REG_SHADOW}} and {{Reg|REG_NOSHADOW}} registers ([[system latch]]). | Each color component has its own set of 7 resistors. 6 of them are used for the actual color value (5 + 1 [[Colors|common bit]]). The last (SHADOW signal) is related to the {{Reg|REG_SHADOW}} and {{Reg|REG_NOSHADOW}} registers ([[system latch]]). | ||
Latest revision as of 23:14, 16 May 2020
The NeoGeo uses a discrete video Digital-to-Analog Converter made of resistors fed by two 74LS273 latches which store the color value from the palette RAM and 74LS05 inverters. This is controlled by either NEO-B1, NEO-GRC or NEO-GRZ.
Note: The schematic has a typo and shows a 74LS06 instead of 74LS05 but both can be used.
Each color component has its own set of 7 resistors. 6 of them are used for the actual color value (5 + 1 common bit). The last (SHADOW signal) is related to the REG_SHADOW and REG_NOSHADOW registers (system latch).
Arcade
The output isn't lowered like on the AES. It goes straight to the JAMMA edge as a 0~3.5V signal for the high-impedance inputs on arcade monitors.
Home
The output is divided by 2200 / (6800 + 2200) = 4.1 to obtain a ~0.9Vp-p max signal, which feeds the video encoder for amplification and conversion to composite.