NEO-G0: Difference between revisions

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[[File:Aes_g0.jpg|right|thumb|NEO-G0 chip found on an AES board.]]
{{ChipInfo
|picture=Aes_g0.jpg
|pkg=QFP64R
|manu=fujitsu
|date=1992 ?
|gates=
|used_on={{PCB|MV2B}} ...
}}


Gates the [[68k]] data bus to the memory card slot and palette RAM. Only found in AES systems ?
Quadruple 245 with additional OR and AND gates. Predecessor of {{Chipname|NEO-BUF}}.


PROG B22 (AES cart ROMOE ?) = ROMOEU AND ROMOEL like in [[NEO-E0]] ?
=Internal logic=


PALWE = PAL OR R/W.
Schematic is wrong: A and B sides are flipped !


=Pinout=
{|
|
[[File:neo-g0_internal.png]]
|
*Pin 51 is enable for MCD0~MCD15
*Pin 39 is enable for PALD0~PALD15
*Pin 40 is direction select for D0~D7
*Pin 52 is direction select for D8~D15
|}


[[File:Neo-g0_pinout.png]]
=Pinouts=


*D0~D15: 68k data bus
==AES==
*PALD0~PALD7: lower byte of palette data
 
*PAUD0~PAUD7: upper byte of palette data
Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.
*MCD0~MCD15: memory card data bus
 
{|
|
{{Pinout|NEO-G0_aes|512}}
|
*D0~D15: [[68k]] data bus
*PALD0~PALD7: Lower [[palette RAM]] data bus
*PAUD0~PAUD7: Upper palette RAM data bus
*MCD0~MCD15: [[Memory card]] data bus
 
*PAL: Palette RAM address decode from [[NEO-C1]]
*R/W: R/W from 68k
*PALWE: Palette RAM /WE, output made from PAL OR R/W
 
*ROMOEL, ROMOEU: from PRO-C0
*ROMOE: Cartridge [[P ROM]] /OE, output made from ROMOEU AND ROMOEL
|}
 
<div style="clear: left;"></div>
 
==MV2B==
 
<gallery>
File:Neo-g0_J4_pinout.png|J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from [[NEO-I0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J4.odg]]
File:Neo-g0_J12_pinout.png|J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from [[NEO-F0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_J12.odg]]
File:Neo-g0_C7_pinout.png|B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from [[PRO-C0]]. OpenOffice Draw file: [[File:neo-g0_mv2b_C7.odg]]
</gallery>


[[Category:Chips]]
[[Category:Chips]]

Latest revision as of 19:35, 2 May 2020

Package QFP64R
Manufacturer
First use 1992 ?
Used on MV2B ...

Quadruple 245 with additional OR and AND gates. Predecessor of NEO-BUF.

Internal logic

Schematic is wrong: A and B sides are flipped !

  • Pin 51 is enable for MCD0~MCD15
  • Pin 39 is enable for PALD0~PALD15
  • Pin 40 is direction select for D0~D7
  • Pin 52 is direction select for D8~D15

Pinouts

AES

Palette RAM and memory card access. Palette RAM /WE and P1 ROM /OE generation.


Edit this pinout

  • D0~D15: 68k data bus
  • PALD0~PALD7: Lower palette RAM data bus
  • PAUD0~PAUD7: Upper palette RAM data bus
  • MCD0~MCD15: Memory card data bus
  • PAL: Palette RAM address decode from NEO-C1
  • R/W: R/W from 68k
  • PALWE: Palette RAM /WE, output made from PAL OR R/W
  • ROMOEL, ROMOEU: from PRO-C0
  • ROMOE: Cartridge P ROM /OE, output made from ROMOEU AND ROMOEL

MV2B

  • J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from NEO-I0. OpenOffice Draw file: File:Neo-g0 mv2b J4.odg

    J4: 68k data bus access for both slots. DS0,DS1: Slot 68k data enables from NEO-I0. OpenOffice Draw file: File:Neo-g0 mv2b J4.odg

  • J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from NEO-F0. OpenOffice Draw file: File:Neo-g0 mv2b J12.odg

    J12: ADPCM buses access for both slots. 10 AS04: negated /ROE from YM2610, 12 AS04: negated /POE from YM2610. SLOT0, SLOT1: enables from NEO-F0. OpenOffice Draw file: File:Neo-g0 mv2b J12.odg

  • B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from PRO-C0. OpenOffice Draw file: File:Neo-g0 mv2b C7.odg

    B7: Palette RAM and memory card access. Palette RAM /WE and System ROM /OE generation. 28 C0 (PAL ?):Palette RAM address decode from PRO-C0. OpenOffice Draw file: File:Neo-g0 mv2b C7.odg

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