LSPC2-A2

LSPC2-A2 graphics chip found in an AES system.

The LSPC chips are only found in cartridge systems.

• Generates S ROM, C ROM and LO ROM addresses based on current display line and VRAM content
• Sync output
• 68k IRQs
• 68k VRAM access

LSPC-A0 chips can be found on early MVS slots and AES systems and work alongside the PRO-B0 chip. LSPC2-A2 chips are found in second revision systems and work with the NEO-B1 chip. The chips figure out what's needed from each type of video ROM on each scanline and the data outputs are fed to the Bx chip for pixel output.

Graphics

Two separate buses run in parallel to fetch data from VRAM for rendering the screen. Each bus connects to a pair of 8bit chips, forming a 16bit bus.

• VRAM 0000-7FFF - 2x 62256/43256 (120ns(?) or faster)
• VRAM 8000-87FF - 2x 5814/5863/6116 (45ns or faster)

The LSPC arbitrates all VRAM access and allows for 68k access at any time during rendering without display glitches. The interface is slow and data writes are ignored when games write VRAM too quickly, especially with overclocked systems *specifics go here maybe*.

It shares a 24bit bus (P0~P23) with the NEO-B1 which goes out to the CHA connector on the cart slot for addressing S ROMs, C ROMs and the on-board LO ROM.

IRQ

All 3 68k interrupts are generated by this chip.

Pinout

(Max size:File:lspc2-a2_pinout.png)
File:Lspc2-a2 pinout.png

OpenOffice Draw file: File:Lspc2-a2.odg

Need to find: 28,87,128,133

• A1~A3: 68k address bus
• D0~D15: 68k data bus
• B0~B14: VRAM bank 0 address bus
• E0~E15: VRAM bank 0 data bus
• C0~C10: VRAM bank 1 address bus
• F0~F15: VRAM bank 1 data bus
• P0~P23: "Internal" multiplexed bus
• /BOE,/BWE: VRAM bank 0 read/write
• /CWE: VRAM bank 1 write enable
• /LSPOE,/LSPWE: Chip read/write (VRAM access,...)
• /RES: Reset
• 1H1:
• 2H1: S ROM A3
• 24M: 24MHz clock input from NEO-D0
• 4M: 4MHz clock output to Z80
• CC4: C ROM A4
• DIVI/DIVO: Frequency divider ?
• DOTA/DOTB,H,LOAD: C ROM multiplexer control, see NEO-ZMC2
• EVEN1/EVEN2:
• INT:
• IP0/IP1:
• PK1: Clock to latch C ROM address from multiplexed bus
• PK2: Clock to latch S ROM address from multiplexed bus
• REF:
• RESETF:
• SCH?:
• SL1?/SL2?:
• SW?:148?
• SYNC:
• TST:
• TST0:
• VCS:
• WE1~WE4,CK1~CK4,SS1,SS2: NEO-B1 communication
• ?NK2:
• CM?L: