68k interrupts

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There are 3 interrupt levels on the AES and MVS, and 4 on the CD hardware.

Interrupts need to be acknowledged by writing to register Reg.png REG_IRQACK.

  • bit 2: Acknowledge vblank interrupt
  • bit 1: Acknowledge timer interrupt
  • bit 0: Acknowledge cold start interrupt

Multiple bits can be set:

move	#$0007,REG_IRQACK     ; Acknowledge all interrupts

Bits 8~10 of the SR register can be used to mask them.

move	#$2000,SR     ; Enable all interrupts (+Supervisor mode)
move	#$2700,SR     ; Disable all interrupts (+Supervisor mode)

Vertical blank interrupt

The vblank interrupt is almost always used. It occurs when the rendering of a frame finishes (~60 times per second). See display timing.

Timer interrupt

The timer interrupt's behavior can be programmed through the GPU's memory mapped registers. It is triggered by a 32-bit down counter clocked by the 6MHz pixel clock, and a corresponding reset register. When the counter reaches 0, an interrupt is generated. Intervals can range from 166.7ns (dangerous interrupt flood) to 11.9 minutes (?).

It can be used for special video effects such as scanline effects, for example:

AES/MVS interrupt levels

  • Vblank: Level 0
  • Timer: Level 1
  • Pending after cold reset: Level 2

CD interrupt levels

  • VBlank: Level 1 !
  • Timer: Level 0 !
  • CDC interrupt: Level 3 !

Level 2 isn't used ?