NEO-I0: Difference between revisions

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*A0~A3,A7: [[68k]] address bus
*A0~A3,A7: [[68k]] address bus
*P0~P15: [[GPU]] multiplexed bus
*P0~P15: [[GPU]] multiplexed bus
*Q00~Q18: [[SFIX]] ROM address lines
*Q01~Q18: [[SFIX]] ROM address lines
*SM1CS(ORO0): [[SM1]] ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
*SM1CS(ORO0): [[SM1]] ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
*SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)
*SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)

Revision as of 23:29, 15 January 2016

NEO-I0 chip found on a MV2B MVS board.

MVS specific chip that does a bunch of unrelated things.

  • S ROM 16bit address latch for SFIX, same as S ROM portion of NEO-273
  • SM1 /CS output when Z80 is reading from ROM and onboard ROMs are enabled
  • /ROMOE output for cartridge(s) PROG board
  • Video sync inversion (or not) to JAMMA edge
  • Coin counter and coin lockout output

Why is A3 needed ?

Pinout

File:Neo-i0 pinout.png

OpenOffice Draw file: File:Neo-i0.odg

  • A0~A3,A7: 68k address bus
  • P0~P15: GPU multiplexed bus
  • Q01~Q18: SFIX ROM address lines
  • SM1CS(ORO0): SM1 ROM chip select, made from SYSTEM(ORI0) OR SDROM(ORI1)
  • SYNCOUT = SYNCIN XOR SYNCREV (SYNCREV always tied to ground ?)
  • Q21, Q22: METER1, METER2
  • Q23, Q24: LOCK1, LOCK2
  • DS0, DS1: Data select for 2-slot systems made from SLOT0, SLOT1, PORTADRS and ROMOE, goes to a NEO-G0
  • CUNTOUT: Address decode from NEO-F0
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