Display timing: Difference between revisions

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[[File:disp.png|right|frame]]
[[File:disp.png|right|frame|This needs to be redone.]]
In NTSC mode, the display is 320x224 pixels. In PAL mode, it is 320x256 pixels.
 
In NTSC mode, the display is 320x224 pixels. In PAL mode, it is 320x256 pixels (16 pixels more at the top and bottom).


Upper 9 bits of register {{Reg|REG_LSPCMODE}}:
Upper 9 bits of register {{Reg|REG_LSPCMODE}}:
*$00F8-$00FF : Vertical sync (8)
*$00F8-$00FF : Vertical sync (8px)
*$0100-$010F : Top border (16)
*$0100-$010F : Top border (16px)
*$0110-$01EF : Active display (224)
*$0110-$01EF : Active display (224px)
*$01F0-$01FF : Bottom border (16)
*$01F0-$01FF : Bottom border (16px)
 
Corrected from and added on to mvstech.txt (by Charles MacDonald). mclk refers to the 24MHz master clock. A pixel is output every 4 mclk.
 
== Horizontal timing ==


From mvstech.txt (by Charles MacDonald):
[[File:Timing_video_lines.png]]
<pre>
[[File:Timing_video_hblank.png]]
Measured in reference to main 24 MHz clock (mclk):


Horizontal timing
*112 mclks (28px) H-sync
*112 mclks (28px) back porch
*1280 mclks (320px) active display
*32 mclks (8px) front porch
*256 mclks (64px) total horizontal blanking
*1536 mclks (384px) total per scanline


Pulse widths:                                 
CHBL tells [[NEO-B1]] to output color 15 of palette 255 ($FFF), which is the [[palettes|backdrop color]].
  111 mclks horizontal sync                    27.75 pixels
  256 mclks horizontal blanking                  64 pixels
1280 mclks active display                      320 pixels
1536 mclks per scanline                        384 pixels


State to state timing:
[[File:Timing_video_vblank.png]]
  118 mclks /HSYNC rising to /HBLANK rising    29.5 pixels (left border)
1280 mclks /HBLANK rising to /HBLANK falling    320 pixels (display)
  27 mclks /HBLANK falling to /HSYNC falling  6.75 pixels (right border)
  111 mclks /HSYNC falling to /HSYNC rising    27.75 pixels (horizontal sync)


384 pixels per scanline: (rounding up)
BNKB (blanking to 0V) changes state 14px after H-sync (middle of the back porch)


  28 pixels horizontal sync pulse width
==Vertical timing==
  29 pixels /HSYNC low to /HBLANK high
320 pixels /HBLANK high to /HBLANK low
  7 pixels /HBLANK low to /HSYNC low


Vertical timing
There are 264 scanlines per frame:


264 scanlines per frame:
*8 scanlines vertical sync pulse
*16 scanlines top border (visible in PAL)
*224 scanlines active display
*16 scanlines bottom border (visible in PAL)


  8 scanlines vertical sync pulse
==Frame timing==
  16 scanlines top border
224 scanlines active display
  16 scanlines bottom border


Frame timing
The exact framerate is 6 MHz / 384 / 264 = 59.18 Hz


Frame rate is 6 MHz / 384 / 264 = 59.18 Hz.
</pre>
</pre>


[[Category:Video system]]
[[Category:Video system]]

Revision as of 06:44, 26 December 2013

File:Disp.png
This needs to be redone.

In NTSC mode, the display is 320x224 pixels. In PAL mode, it is 320x256 pixels (16 pixels more at the top and bottom).

Upper 9 bits of register REG_LSPCMODE:

  • $00F8-$00FF : Vertical sync (8px)
  • $0100-$010F : Top border (16px)
  • $0110-$01EF : Active display (224px)
  • $01F0-$01FF : Bottom border (16px)

Corrected from and added on to mvstech.txt (by Charles MacDonald). mclk refers to the 24MHz master clock. A pixel is output every 4 mclk.

Horizontal timing

  • 112 mclks (28px) H-sync
  • 112 mclks (28px) back porch
  • 1280 mclks (320px) active display
  • 32 mclks (8px) front porch
  • 256 mclks (64px) total horizontal blanking
  • 1536 mclks (384px) total per scanline

CHBL tells NEO-B1 to output color 15 of palette 255 ($FFF), which is the backdrop color.

BNKB (blanking to 0V) changes state 14px after H-sync (middle of the back porch)

Vertical timing

There are 264 scanlines per frame:

  • 8 scanlines vertical sync pulse
  • 16 scanlines top border (visible in PAL)
  • 224 scanlines active display
  • 16 scanlines bottom border (visible in PAL)

Frame timing

The exact framerate is 6 MHz / 384 / 264 = 59.18 Hz