Display timing

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This needs to be redone.

In NTSC mode, the display is 320x224 pixels. In PAL mode, it is 320x256 pixels (16 pixels more at the top and bottom).

Upper 9 bits of register Reg.png REG_LSPCMODE:

  • $00F8-$00FF : Vertical sync (8px)
  • $0100-$010F : Top border (16px)
  • $0110-$01EF : Active display (224px)
  • $01F0-$01FF : Bottom border (16px)

Corrected from and added on to mvstech.txt (by Charles MacDonald). mclk refers to the 24MHz master clock. A pixel is output every 4 mclk.

Notes: After RESET, SYNC goes high after 1399 mclk (falling edge). 112 mclk high. 1424 mclk low. 1536 mclk total. 112mclk low = 28px, 59 mclk = 14.75px, high before RESET (vblank, sync is inverted).

Horizontal timing

Timing video lines.png Timing video hblank.png

  • 112 mclks (28px) H-sync
  • 112 mclks (28px) back porch
  • 1280 mclks (320px) active display
  • 32 mclks (8px) front porch
  • 256 mclks (64px) total horizontal blanking
  • 1536 mclks (384px) total per scanline

CHBL tells NEO-B1 to output color 0 of palette 0, which is the reference color.

Timing video vblank.png

BNKB (blanking to 0V) changes state 14px after H-sync (middle of the back porch)

Vertical timing

There are 264 scanlines per frame:

  • 8 scanlines vertical sync pulse
  • 16 scanlines top border (visible in PAL)
  • 224 scanlines active display
  • 16 scanlines bottom border (visible in PAL)

Frame timing

See framerate.